• Korean Chemical Engineering Research
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• v.62 no.1
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• pp.1-6
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• 2024

As the demand for hydrogen electric vehicles for commercial vehicles increases, the durability of PEMFCs must increase more than five times that of passenger cars, so research and development to improve durability is urgent. When the PEMFC membrane electrode assembly (MEA) undergoes chemical degradation, the MEA thickness decreases and pinholes occur. In this study, changes in the performance and durability of the MEA were measured while increasing the clamping pressure of the unit cell after open circuit voltage (OCV) holding, an accelerated chemical degradation experiment. As the clamping pressure increased, the resistance of the polymer membrane and the membrane/electrode contact resistance decreased, improving the I-V performance and reducing the hydrogen permeability. As the hydrogen permeability decreased, the OCV increased. When the pinhole area was removed and the MEA clamping pressure was increased, the hydrogen permeability decreased sharply, confirming that the local degradation has a large effect on the performance and durability of the entire cell. When the pinhole was removed and re-clamping and OCV holding was evaluated, it was confirmed that the durability improved according to the decrease in membrane resistance and hydrogen permeability.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.122-130
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• 2013

This work proposes a 12b 100MS/s 45nm CMOS four-step pipeline ADC for high-speed digital communication systems requiring high resolution, low power, and small size. The input SHA employs a gate-bootstrapping circuit to sample wide-band input signals with an accuracy of 12 bits or more. The input SHA and MDACs adopt two-stage op-amps with a gain-boosting technique to achieve the required DC gain and high signal swing range. In addition, cascode and Miller frequency-compensation techniques are selectively used for wide bandwidth and stable signal settling. The cascode current mirror minimizes current mismatch by channel length modulation and supply variation. The finger width of current mirrors and amplifiers is laid out in the same size to reduce device mismatch. The proposed supply- and temperature-insensitive current and voltage references are implemented on chip with optional off-chip reference voltages for various system applications. The prototype ADC in a 45nm CMOS demonstrates the measured DNL and INL within 0.88LSB and 1.46LSB, respectively. The ADC shows a maximum SNDR of 61.0dB and a maximum SFDR of 74.9dB at 100MS/s, respectively. The ADC with an active die area of $0.43mm^2$ consumes 29.8mW at 100MS/s and a 1.1V supply.