• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.7C
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• pp.706-712
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• 2006

In this letter, we propose a compact CORDIC processor for implementation of carrier frequency synchronization block in an OFDM (Orthogonal Frequency Division Multiplexing) system. The compact CORDIC processor is proposed by using inherenct properties of an OFDM system for estimation and compensation of carrier frequency offset, and is composed of a compact CORDIC preprocessor and a compact CORDIC processor. The compact CORDIC preprocessor plays a role of normalizing input signal efficiently, and the compact CORDIC processor is proposed to perform the vectoring mode and rotational mode jointly in CORDIC operation for carrier frequency synchronization. It is shown by FPGA implementation that the proposed compact CORDIC processor can achieve better performance with a significantly reduced hardware complexity than the conventional CORDIC approach.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.1
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• pp.6-14
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• 2011

This paper presents a high-speed QR decomposition architecture for the multi-input-multi-output (MIMO) receiver based on Givens rotation. Under fast-varying channel, since the inverse matrix calculation has to be performed frequently in MIMO receiver, a high performance and low latency QR decomposition module is highly required. The proposed QR decomposition architecture is composed of Sign-Select Lookahead (SSL) coordinate rotation digital computer (CORDIC). In the SSL-CORDIC, the sign bits, which are computed ahead to select which direction to rotate, are used to select one of the last iteration results, therefore, the data dependencies on the previous iterations are efficiently removed. Our proposed QR decomposition module is implemented using TSMC 0.25 ${\mu}M$ CMOS process. Experimental results show that the proposed QR architecture achieves 34.83% speed-up over the Compact CORDIC based architecture for the 4 ${\times}$ 4 matrix decomposition.