• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.1
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• pp.117-122
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• 2016

In this paper, we propose 24-GHz CMOS radio frequency (RF) power amplifier for short-range automotive collision avoidance radars. This circuit contains common source stage with inter-stages conjugate matching circuit as a class-A mode amplifier. The proposed circuit is designed using TSMC $0.13-{\mu}m$ mixed signal/RF CMOS process ($f_T/f_{MAX}=120/140GHz$). It operates at the supply voltage of 2V, and it is designed to have high power gain, low insertion loss and low noise figure in the low supply voltage. To reduce total chip area, the circuit used transmission lines instead of the bulky real inductor. The designed CMOS power amplifier showed the smallest chip size of $0.1mm^2$, the lowest power consumption of 40mW, the highest power gain of 26.5dB, the highest saturated output power of 19.2dBm and the highest maximum power-added efficiency of 17.2% as compared to recently reported results.

• The Transactions of the Korean Institute of Power Electronics
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• v.3 no.4
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• pp.315-322
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• 1998

Power conversion system must increase switching frequency in order to achieve small size, light weight and low noise. However, the switches of converter are subject to high switching power losses and switching stresses. As a result, the power system has a lower efficiency. In this paper, the authors propose an AC-DC boost converter of high efficiency by partial resonant switching mode. The switching devices in the proposed circuit are operated with soft switching and the control technique of those is simplified for switch to drive in constant duty cycle. The partial resonant circuit makes use of a inductor using step up and a condenser of loss-less snubber. Besides, by regenerating energy, that is charged in a loss less snubber condenser of a snubber adopted to a common circuit, toward an input source part, this circuit can get increased efficiency. as merit. The result is that the switching loss is very low, the efficiency and power factor of system is high. The proposed converter is deemed the most suitable for high power applications where the power switching devices are used.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.4
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• pp.1903-1907
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• 2013

Heart condition should be observed for long periods of time because it does not appear abnormal all the time. However, there are many difficulties checking our health for a long time due to its size, operation of equipment, and cost. To solve these problems, an electrocardiograms(ECG), specially interfacing three gel-less metal electrodes for low cost portable applications, is designed and implemented. Gel-less metal electrodes are used for ECG monitoring system instead of gel-type electrodes that can cause skin rashes and itching problem. The whole ECG system consists of two parts-analog and digital circuits. The analog measurement circuit that has a 18*25mm size is made up of op-amps maintaining a sufficiently high common-mode noise rejection and passive elements of SMD type. Analog heart signal is converted to digital stream suitable for display on a TFT-LCD by an 8-bit microcontroller. The size of the completed ECG system is 25*80*50mm and its weighing is about 150g, which is small enough to be easily used. Therefore, the implemented ECG system can be used as a portable one.

• Smart Structures and Systems
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• v.24 no.3
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• pp.333-343
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• 2019

The possibility of adopting vibration-powered wireless nodes has been largely investigated in the last years. Among the available technologies based on the piezoelectric effect, the most common ones consist of a vibrating beam covered by electroactive layers. Another energy harvesting strategy is based on the use of piezoelectric strips attached to a hosting structure subjected to dynamic loads. The hosting structure, for example, can be the system to be equipped with wireless nodes. Such strategy has received few attentions so far and no analytical studies have been presented yet. Hence, the original contribution of the present paper is concerned with the development of analytical solutions for the electrodynamic analysis and design of piezoelectric polymeric strips attached to relatively large linear elastic structural systems subjected to random vibrations at the base. Specifically, it is assumed that the dynamics of the hosting structure is dominated by the fundamental vibration mode only, and thus it is reduced to a linear elastic single-degree-of-freedom system. On the other hand, the random excitation at the base of the hosting structure is simulated by filtering a white Gaussian noise through a linear second-order filter. The electromechanical force exerted by the polymeric strip is negligible compared with other forces generated by the large hosting structure to which it is attached. By assuming a simplified electrical interface, useful new exact analytical expressions are derived to assess the generated electric power and the integrity of the harvester as well as to facilitate its optimum design.

• Journal of Broadcast Engineering
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• v.24 no.6
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• pp.1035-1052
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• 2019

Recently, as the demand for immersive videos increases, efficient video processing techniques for omnidirectional immersive video is actively developed by MPEG-I. While the omnidirectional video provides a larger degree of freedom for a free viewpoint, the size of the video increases significantly. Furthermore, in order to compress 6 degree-of-freedom (6 DoF) videos that support motion parallax, it is required to develop a codec to yield better coding efficiency. In this paper, we develop a 6 DoF codec using Versatile Video Coding (VVC) as the next generation video coding standard. To the authors' best knowledge, this is the first VVC-based 6 DoF video codec toward the future ISO/IEC 23090 Part 7 (Metadata for Immersive Media (Video)) MPEG-I standardization. The experiments were conducted on the seven test video sequences specified in Common Test Condition (CTC) in two operation modes of TMIV (Test Model for Immersive Media) software. It is demonstrated that the proposed codec improves coding performance around 33.8% BD-rate reduction in the MIV (Metadata for Immersive Video) mode and 30.2% BD-rate reduction in the MIV view mode as compared to the state-of-the-art TMIV reference software. We also show the performance comparisons using Immersive Video PSNR (IV-PSNR) and Mean Structural Similarity (MSSIM).

• Progress in Superconductivity
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• v.5 no.1
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• pp.50-54
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• 2003

We have fabricated $∂^2$$B_{z}$ /$∂x^2$ type planar gradiometers and studied their properties in operation under various field conditions. $YBa_2$$Cu_3$$O_{7}$ film was deposited on $SrTiO_3$ (100) substrate by a pulsed laser deposition (PLD) system and patterned into a device by the photolithography with ion milling technique. The device consists of 3 pickup loops designed symmetrically Inner dimension and the width of the square side loops are 3.6 mm and 1.2 mm, respectively, and the corresponding dimensions of the center loop are 2.0 mm and 1.13 mm. The length of baseline gradiometer is 5.8 mm. Step-edge junction width is 3.0 $\mu\textrm{m}$ and the hole size of the SQUID loop is 3 $\mu\textrm{m}$ ${\times}$ 52 $\mu\textrm{m}$. The SQUID inductance is estimated to be 35 pH. The device was formed on a 20 mm ${\times}$ 10 mm substrate. We have tested the behavior of the device in various field conditions. The unshielded gradiometer was stable under extremely hostile conditions on a laboratory bench. Noise level 0.45 pT/$\textrm{cm}^2$/(equation omitted)Hz and 0.84 pT/$\textrm{cm}^2$/(equation omitted)Hz at 1 Hz for the shielded and the unshielded cases, which correspond to equivalent field noises of 150 fT/(equation omitted)Hz and 280 fT/(equation omitted)Hz, respectively. In spite of the short baseline of 5.8 mm, the high common-mode-rejection-ratio of the gradiometer, $10^3$, allowed us to successfully record magnetocardiogram of a human subject, which demonstrates the feasibility of the design in biomagnetic studies.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.3
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• pp.184-196
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• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for precision measurement of current flowing through a secondary cell battery in a battery management system (BMS). The proposed modulator implements two switched capacitor integrators and a single-bit comparator with peripheral circuits such as a non-overlapping clock generator and a bias circuit. The proposed structure is designed to be applied to low-side current sensing method with low common mode input voltage. Using the low-side current measurement method has the advantage of reducing the burden on the circuit design. In addition, the ±30mV input voltage is resolved by the ADC with 15-bit resolution, eliminating the need for an additional programmable gain amplifier (PGA). The proposed a single-bit 2nd-order delta-sigma modulator has been implemented in a 350-nm CMOS process. It achieves 95.46-dB signal-to-noise-and-distortion ratio (SNDR), 96.01-dB spurious-free dynamic range (SFDR), and 15.56-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 400 for 5-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 670×490 ㎛2 and 414 ㎼, respectively.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.6
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• pp.454-464
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• 2023

This paper proposes a low-power 8-bit asynchronous SAR ADC with a sampling rate of 1 MS/s for sensor node applications. The ADC uses bootstrapped switches to improve linearity and applies a VCM-based CDAC switching technique to reduce the power consumption and area of the DAC. Conventional synchronous SAR ADCs that operate in synchronization with an external clock suffer from high power consumption due to the use of a clock faster than the sampling rate, which can be overcome by using an asynchronous SAR ADC structure that handles internal comparisons in an asynchronous manner. In addition, the SAR logic is designed using dynamic logic circuits to reduce the large digital power consumption that occurs in low resolution ADC designs. The proposed ADC was simulated in a 180-nm CMOS process, and at a 1.8 V supply voltage and a sampling rate of 1 MS/s, it consumed 46.06 𝜇W of power, achieved an SNDR of 49.76 dB and an ENOB of 7.9738 bits, and obtained a FoM of 183.2 fJ/conv-step. The simulated DNL and INL are +0.186/-0.157 LSB and +0.111/-0.169 LSB.