• The Transactions of the Korean Institute of Electrical Engineers B
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• v.48 no.2
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• pp.89-96
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• 1999

This paper proposes a common-mode voltage reduction method base on SVPWM(Space-Vector Pulsewidth Modulation) in three phase PWM converter/inverter system. By shifting the active voltage vector of inverter and aligning this to the active vector of converter, it is possible to eliminate a common-mode voltage pulse in one control period. Since the proposed PWM method maintains the active voltage vector, it does not affect the control performance of PWM converter/inverter system. Without any extra hardware, overall common mode voltage dv/dt and conrresponding leakage current can be reduced to two-third of the conventional three phase symmetric SVPWM scheme.

• Journal of Power Electronics
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• v.12 no.4
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• pp.548-558
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• 2012

In this paper, a novel offset-based single-state pulse width modulation (PWM) method for achieving zero common-mode voltage (CMV) and reducing switching losses in multilevel inverters is presented. The specific active switching state of the zero common-mode (ZCM) voltage that approximates the reference voltage can be deduced from the switching state sequence of the reduced CMV phase disposition PWM (CMV PD PWM) method. From the reference leg voltages for the zero common-mode voltage, an N-to-2-level transformation defines a virtual two-level inverter and the corresponding nominal leg voltage references. The commutation process of the reduced CMV PD PWM method in a multilevel inverter and its outputs can be simply followed in a nominal switching time diagram for the virtual inverter. The characteristics of the reduced CMV PD PWM and the single-state PWM for zero common-mode voltage are analyzed in detail in this paper. The theoretical analysis of the proposed PWM method is verified by experimental results.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1652-1653
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• 2011

This paper builds a printed circuit board to calculate the radiated emissions due to the common-mode and differential-mode currents. The calculated results agree with the measured values. Based on the calculated values, it is shown clearly that the common-mode radiations are the dominator of the radiated emissions from the device. The radiated emissions due to the common-mode currents can easily dominate the radiated emissions from the printed circuit board.

• The Transactions of the Korean Institute of Power Electronics
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• v.5 no.5
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• pp.443-450
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• 2000

A PWM inverter for an induction motor often has a problem with a high frequency leakage current that flows through stray capacitors between stator windings and a motor frame to ground. This paper proposes a new type of Active Common Mode Voltage Canceler circuit for the reduction of common mode voltage and high frequency leakage current generated by the PWM VSI-fed induction motor drives. The compensating voltage applied by the common made voltage canceler has the same amplitude as, hut the opposite polarity to, the common mode voltage by PWM Inverter. Therefore, common mode voltage and high frequency leakage current can be canceled. The proposed circuit consists of four-level half-bridge inverter and common-mode transformer. Simulated and experimental results show that common mode voltage canceler makes significant contributions to reducing a high frequency leakage current.

• Journal of Power Electronics
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• v.19 no.6
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• pp.1582-1590
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• 2019

A new method for reducing the common-mode current generated by the voltage variations in a two-inverter air conditioner system by applying a synchronized pulse-width modulation (PWM) strategy is proposed. The PWM signals of the master-mode inverter are generated based on the reference voltage, while those of the slave-mode inverter are output in the opposite direction when the master-mode inverter changes its switching state. However, the slave-mode control results in a mismatch between the reference voltage and the actual output voltage that is modified by synchronized control operation. The proposed method is capable of reducing and controlling this voltage error by performing signal selection in the vector space of the slave-mode inverter, which mitigates the distortion of the phase current. The efficacy of this method in reducing conducted emissions has been validated both theoretically and experimentally.

• Transactions of the Korean Society of Automotive Engineers
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• v.11 no.5
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• pp.43-49
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• 2003

The common-rail fuel injection system is becoming a common technology for High Speed Direct Injection(HSDI) diesel engines. The injection timing and rate are important factors for combustion control and pollutants formation mechanisms during engine operation. This paper introduces an estimation methodology of the injection timing and rate of a common-rail injector for HSDI diesel engines. A sliding mode observer that is based on the nonlinear mathematical model of the common-rail injector is designed to overcome the model uncertainties. The injector model and the estimator we verified by relevant injection experiments in an injector test bench. The simulation and the experimental results show that the proposed sliding mode observer can effectively estimate the injection rate of the common-rail injector.

• Journal of Advanced Navigation Technology
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• v.17 no.2
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• pp.196-201
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• 2013

In this paper, a dual-mode balanced filter with symmetric coupled composite right/left-handed transmission line is introduced. Unlike the other symmetric structure, this configuration has the ability to operate under both common- and differential-mode excitation. These properties are achievable through providing physical short circuit by means of ground vias at the center of each unit-cell along the symmetry plane of the structure. Because the CRLH unit-cells are operated under both common- and differential-mode excitation, we implemented a balanced filter using these properties. To validity these features, a five-cell four port coupled CRLH-TL is simulated, fabricated and measured and the obtained performances agree with the simulation results under both common- and differential-mode excitation.

• Journal of Power Electronics
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• v.19 no.3
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• pp.727-743
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• 2019

This paper presents a pulse-width modulation strategy to eliminate the common mode voltage (CMV) with reduced CMV spikes in multilevel inverters since a high CMV magnitude and its fast variations dv/dt result in bearing failure of motors, overvoltage at motor terminals, and electromagnetic interference (EMI). The proposed method only utilizes the zero CMV states in a space vector diagram and it is implemented by a carrier-based pulse-width modulation (CBPWM) method. This method is generalized for odd number levels of inverters including neutral-point-clamped (NPC) and cascaded H-bridge inverters. Then it is extended to the over-modulation mode. The over-modulation mode is implemented by using the two-limit trajectory principle to maintain linear control and to avoid look-up tables. Even though the CMV is eliminated, CMV spikes that can cause EMI and bearing current problems still exist due to the deadtime effect. As a result, the deadtime effect is analyzed. By taking the deadtime effect into consideration, the proposed method is capable of reducing CMV spikes. Simulation and experimental results verify the effectiveness of the proposed strategy.

• Journal of Power Electronics
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• v.14 no.2
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• pp.315-323
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• 2014

An optimized space vector pulse width modulation (SVPWM) method with common mode voltage elimination and neutral point potential balancing is proposed for an open-end winding induction motor. The motor is fed from both of the ends with two neutral point clamped (NPC) three-level inverters. In order to eliminate the common mode voltage of the motor ends and balance the neutral point potential of the DC link, only zero common mode voltage vectors are used and a balancing control factor is gained from calculation in the strategy. In order to improve the harmonic characteristics of the output voltages and currents, the balancing control factor is regulated properly and the theoretical analysis is provided. Simulation and experimental results show that by adopting the proposed method, the common mode voltage can be completely eliminated, the neutral point potential can be accurately balanced and the harmonic performance for the output voltages and currents can be effectively improved.

• The Transactions of the Korean Institute of Power Electronics
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• v.8 no.1
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• pp.89-97
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• 2003

High frequency common mode voltage produced by PWM inverter fed Induction motor is a major cause of conducted EMI, creation motor ground currents, bearing currents and other harmful products. The zero switching states of inverter control invoke large in comparison with the non-zero switching state of Inverter control. We proposed a common mode voltage reduction method based on sinusoidal PWM technique. PWM signal are generated by comparing respective sinusoidal reference signal with three triangular carrier wave displaced of 120$^{\circ}$. Simulation and experimenta1 result show that common mode voltages in the proposed PWM technique are reduced by approximate 66% more than conventional FWM technique.