• Journal of Institute of Control, Robotics and Systems
• /
• v.6 no.2
• /
• pp.228-233
• /
• 2000

It is common to apply the technology of FPGA (Fie이 Programmable Gate Array) which is one of the design methods for ASIC(Application Specific IC)to the active components used in the data processing at the digital system of satellite aircraft missile etc for compact lightness and integration of Printed Circuit Board (PCB) In carrying out the digital data processing the FPGAs are designed for the various functions of the Process Control Interrupt Control Clock Generation Error Detection and Correction (EDAC) as the individual module. In this paper an FPGA chip for Single Error Correction and Double Error Detection (SEC-DED) for EDAC is designed and simulated by using a VLSI design software LODECAP.

• Proceedings of the KIPE Conference
• /
• 1999.07a
• /
• pp.650-654
• /
• 1999

In this paper, author describe the simulation results concerning the period doubling bifurcation route to chaos of DC/DC boost converter under current mode control to show that it is common phenomena on switching regulator when parameters are improperly chosen or continuously varied beyond the ensured region by system designer. Bifurcation diagrams of periodic orbits of inductor current and capacitor voltage of DC/DC boost converter are plotted with sampled data at moment of each clock pulse causing switching on. DC/DC boost converter studied on this paper is modelled by its state space equations as per switching condition under continuous conduction mode. Current reference signal and capacitance are chosen as the bifurcation parameters and those are varied in step for iterative calculation to find bifurcation points of periodic orbits of state variables.

• 제어로봇시스템학회:학술대회논문집
• /
• 1988.10a
• /
• pp.697-700
• /
• 1988

This paper describes the design of a hardware system for ECG feature extraction based on pipeline processor consisting of three computers. ECG data is acquisited by 12 bit A/D converter with hardware QRS triggred detector. Four diagnostic parameters-heart, axis, and ST axis, and ST segment are used for the classification and the diagnosis of arrhythmia. The functions of the main CPU were distributed and processed with three microcomputers. Therefore the effective data process and the real time process using microcomputer can be obtained. The interconnection structure consisting of two common memory units is designed to decrease the delay time caused by data transfer between processors and designed by which the delay time can be taken 1% of one clock period.

• Proceedings of the IEEK Conference
• /
• 2002.07b
• /
• pp.1288-1291
• /
• 2002

In this paper, we present a design of mpeg-4 video codec chip to reduce the power consumption using frame level clock gating and motion estimation skip scheme. It performs 30 grames/s of codec (encoding and decoding) mode with quarter-common intermediate format(QCIF) at 27MHz. A novel low-power techniques were implemented in architectural level, which is 35% of the power dissipation for a conventional CMOS design. This chip performs MPEG-4 Simple Profile Level 2(Simple@L2) and H.263 base mode. Its contains 388,885 gates, 662k bits memory, and the chip size was 9.7 mm x 9.7 mm which was fabricated using 0.35 micron 3-layers metal CMOS technology.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.26 no.8
• /
• pp.1217-1226
• /
• 1989

This paper describes a design of hardware system for real time automatic diagnosis of ECG arrhythmia based on pipeline processor consisting of three microcomputer. ECG data is acquisited by 12 bit A/D converter with hardware QRS triggered detector. Four diagnostic parameters-heart rate, morpholigy, axis, and ST segment-are used for the classification and the diagnosis of arrhythmia. The functions of the main CPU were distributed and processed with three microcomputers. Therefore the effective data process and the real time process using microcomputer can be obtained. The interconnection structure consisting of two common memory unit is designed to decrease the delay time caused by data transfer between processors and be which the delay time can be taken 1% of one clock period.

• Korean Journal of Plant Taxonomy
• /
• v.48 no.1
• /
• pp.1-8
• /
• 2018

Mankyua chejuense is the only member of the monotypic genus Mankyua (Ophioglossaceae) and is endemic to Jejudo Island, Korea. To determine the precise phylogenetic position of M. chejuense, two cpDNA regions of 42 accessions representing major members of lycophytes are obtained from GenBank and analyzed using three phylogenetic analyses (maximum parsimony, maximum likelihood, and Bayesian inference). In addition, the divergence time is estimated based on a relaxed molecular clock using four fossil calibration points. The phylogenetic position of Mankyua still appears to be uncertain, representing either the earliest diverged lineage within Ophioglossaceae or a sister to the clade containing Ophioglossum and Helminthostachys. The most recent common ancestor of Ophioglossaceae and its sister lineage, Psilotum, was estimated to be 256 Ma, while the earliest divergence of Mankyua was estimated to be 195 Ma in the early Jurassic.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.34C no.8
• /
• pp.22-38
• /
• 1997

This paper proposes a new VLSI architecture for morphological filters and presents its chip design and implementation. The proposed architecture can significantly reduce hardware costs compared with existing architecture by using a feedback loop path to reuse partial results and a decoder/encoder pair to detect maximum/minimum values. In addition, the proposed architecture requires one common architecture for both diltion and erosion and fewer number of operations. Moreover, it can be easily extended for larger size morphologica operations. We developed VHDL (VHSIC hardware description language) models, performed logic synthesis using the SYNOPSYS CAD tool. We used the SOG (sea-of-gate) cell library and implemented the actual chip. The total number of gates is only 2,667 and the clock frequency is 30 MHz that meets real-time image processing requirements.

• Journal of Biomedical Engineering Research
• /
• v.9 no.1
• /
• pp.79-86
• /
• 1988

This paper describes the design of a hardware systenl for ECG feature extraction based on pipeline processor consistinsf of three microcomputers. ECG data is acquisited by 12 bit A/D converter with hardware QRS triggered detector. Four diagnostic parameters parameters-heart rate, morPhology, axis, and 57 segment-are used for the classification and the diagnosis of arrhythmia. The functions of the main CPU were distributed and processed with three microcomputers. Therefore the effective data process and the real time process using microcomputer can be obtained. The interconnection structure consisting of two common memory units is designed to decrease the delay time caused by data transfer between processors and designed by which the delay time can be taken Loye of one clock period.

• Journal of the Korean Society for Aviation and Aeronautics
• /
• v.21 no.1
• /
• pp.8-14
• /
• 2013

As GNSS(Global Navigation Satellite System) is used in various filed, many countries establish GNSS system independently. But GNSS system has the limitation of accuracy and stability in stand-alone mode, because this system has error elements which are ionospheric delay, tropospheric delay, orbit ephemeris error, satellite clock error, and etc. For overcome of accuracy limitation, the DGPS(Differential GPS) and RTK(Real-Time Kinematic) systems are proposed. These systems perform relative positioning using the reference and user receivers. ETRI(Electronics and Telecommunications Research Institute) is developing precision navigation system in point of extension of GNSS usage. The precision navigation system is for providing the precision navigation solution to common users. If this technology is developed, GNSS system can be used in the fields which require precision positioning and control. In this paper, we introduce the precision navigation system and perform design and algorithm verification.

• Proceedings of the KIEE Conference
• /
• 1988.07a
• /
• pp.731-733
• /
• 1988

This paper describes a design of hardware system for real time automatic diagnosis of ECG arrhythmia based on pipeline processor consisting of the three microcomputer. ECG data is acquisited by 12 bit A/D converter with hardware QRS triggered detector. Four diagnostic parameters - heart rate, morphology, axis, and ST segment - are used for the classification and the diagnosis of arrhythmia. The functions of the main CPU were distributed and processed with three microcomputers. There-fore the effective data process and the real time process using microcomputer can be obtained. The interconnection structure consisting of two common memory units is designed to decrease the delay time caused by data transfer between processors and by which the delay time can be taken 1 % of one clock period.