• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.2
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• pp.720-726
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• 2010

Haplotype-based research has become increasingly important in the field of personalized medicine since the haplotype reflects a set of SNPs (Single Nucleotide Polymorphisms) that are genetically associated and inherited together. Currently, the most widely used application softwares available for haplotype reconstruction, based on in silico method, include PL-EM, Haplotyper, PHASE and HAP. PL-EM, Haplotyper and PHASE are command-line application running on LINUX or Unix system and HAP is a web-based client-server application. This paper deals with an integrated haplotype reconstruction system that have been developed with PL-EM and Haplotyper selected from the accuracy test with experimentally verified data on public application softwares. This integrated system is a kind of client-sever one with user friendly web interface and can provide end-users with a high quality of haplotype analysis. SNPs genotype data with a length of 5 derived from 5 people and SNPs genotype data with a length of 13 derived from 15 people were used to test the analysis results of Haplotyper and PL-EM respectively. As a result, this system has been confirmed to provide the systematic and easy-to-understand analysis results that consist of two main parts, i.e. individual haplotype information and haplotype pool information. In this respect, the integration system will be utilized as a useful tool for the discovery of disease related genes and the development of personalized drugs through facilitating the reconstruction of haplotype maps.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.39 no.6
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• pp.553-558
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• 2011

This paper describes the development and test result of S-band Transmitter flight model(FM) of STSAT-3 by satellite research center(SaTReC), KAIST. The communication sub-system of STSAT-3 is consist of two different frequency band channels, S-band for Telemetry & Command and X-band for mission data. S-band Transmitter(STX) functionally made of modulator, frequency synthesizer, power amp and DC/DC converter. The transmission data is modulated by FSK(Frequency Shift Keying) and the interface between spacecraft sub-module and STX is RS-422 standard method. The FM STX is based on modular design. The RF output power of STX is 1.5W(31.7dBm) and BER of STX is under $1{\times}10^{-5}$ which meets the specification respectively. The FM STX is delivered Spacecraft Assembly, Integration and Test(AIT) level through the completion of functional Test and environmental(vibration, thermal vacuum) Test successfully.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.1
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• pp.58-62
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• 2007

Digital communication is important for reliability and mobilization of the multi-channel communication systems. Transmitting and receiving data for the mobilization should be possible in anywhere and in anytime. And this system must be designed light weight small size and low power. One are essential technology for implementing the mobile wireless communication system on the age of ubiquotos. Requirements in constructing such communication field are followings. At first data transmitting and receiving should be carried out by a simple command. Second, the device should be designed as hand-hold type and low power consumption. Third, data communication should be reliable. As one of examples, car to car system which is popular in the market is introduced here, All traffic information in highway is transmitted from one car to another by using this system which can prevent possible traffic accident. This paper shows the design of a digital data communication system with CC1020 chip. This CC1020 makes easy frequency selection and easy switch from the transmit mode to the receive mode by simple setting of a memory register in the chip. The transmit power of this system is designed 10dBm and its communication range is about 100m. The power supplied this system is 3V considered as low power. The sleep mode can be easily entered during transmit mode or receive mode. We shows the program algorithm of CC1020 and interface circuit between MCU and CC1020. We shows the Photo of the CC1020 Module and Atmega128 Module.. We analysed the receiver rate with this system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.554-557
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• 2016

Recently, supercomputer has been increasingly adopted as a computing environment for scientific simulation as well as education, healthcare and national defence. Especially, supercomputing system with heterogeneous computing resources is gaining resurgence of interest as a next-generation problem solving environment, allowing theoretical and/or experimental research in various fields to be free of time and spatial limits. However, traditional supercomputing services have only been handled through a simple form of command-line based console, which leads to the critical limit of accessibility and usability of heterogeneous computing resources. To address this problem, in this paper, we provide the design and implementation of web-based HPC (High Performance Computing) job management framework for computational scientific simulation. The proposed framework has highly extensible design principles, providing the abstraction interfaces of job scheduler (as well as bundle scheduler plug-ins for LoadLeveler, Sun Grid Engine, OpenPBS scheduler) in order to easily incorporate the broad spectrum of heterogeneous computing resources such as cluster, computing cloud and grid. We also present the detailed specification of HTTP standard based RESTful endpoints, which manage simulation job's life-cycles such as job creation, submission, control and status monitoring, etc., enabling various 3rd-party applications to be newly created on top of the proposed framework.

• The KIPS Transactions:PartA
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• v.12A no.6 s.96
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• pp.523-530
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• 2005

When a PCI 2.2 bus master requests data using Memory Read command, a target device may hold PCI bus without data to be transferred for long time because a target device needs time to prepare data infernally. Because the usage efficiency of the PCI bus and the data transfer efficiency are decreased due to this situation, the PCI specification recommends to use the Delayed Transaction mechanism to improve the system performance. But the mechanism cann't fully improve performance because a target device doesn't know the exact size of prefetched data. In the previous work, we propose a new method called Prefetch Request when a bus master intends to read data from the target device. In this paper, we design PCI 2.2 controller and local device that support the proposed method. The designed PCI 2.2 controller has simple local interface and it is used to convert the PCI protocol into the local protocol. So the typical users, who don't know the PCI protocol, can easily design the PCI target device using the proposed PCI controller. We propose the basic behavioral verification, hardware design verification, and random test verification to verify the designed hardware. We also build the test bench and define assembler instructions. And we propose random testing environment, which consist of reference model, random generator ,and compare engine, to efficiently verify corner case. This verification environment is excellent to find error which is not detected by general test vector. Also, the simulation under the proposed test environment shows that the proposed method has the higher data transfer efficiency than the Delayed Transaction about $9\%$.

• Journal of Internet Computing and Services
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• v.23 no.5
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• pp.87-101
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• 2022

Cyber-attacks occur in the blink of an eye in cyberspace, and the damage is increasing all over the world. Therefore, it is necessary to develop a cyber common operational picture that can grasp the various assets belonging to the 3rd layer of cyberspace from various perspectives. By applying the method for grasping battlefield information used by the military, it is possible to achieve optimal cyberspace situational awareness. Therefore, in this study, the visualization screens necessary for the cyber common operational picture are identified and the criteria (response speed, user interface, object symbol, object size) are investigated. After that, the framework is designed by applying the identified and investigated items, and the visualization screens are implemented accordingly. Finally, among the criteria investigated by the visualization screen, an experiment is conducted on the response speed that cannot be recognized by a photograph. As a result, all the implemented visualization screens met the standard for response speed. Such research helps commanders and security officers to build a cyber common operational picture to prepare for cyber-attacks.