• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1571-1574
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• 2002

This paper describes a circuit and its operations of a programmable digital on-chip terminator designed with CMOS circuits which are used in high speed I/O interface. The on-chip terminator matches external reference resistor with the accuracy of ${\pm}$ 4.1％ over process, voltage and temperature variation. The digital impedance codes are generated in programmable impedance controller (PIC), and the codes are sent to terminator transistor arrays at input pads serially to reduce the number of signal lines. The transistor array is thermometer-coded to reduce impedance glitches during code update and it is segmented to two different blocks of thermometer-coded transistor arrays to reduce the number of transistors. The terminator impedance is periodically updated during hold time to minimize inter-symbol interferences.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.320-322
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• 2002

A new simple spatial scheme for base station with adaptive antenna in Code Division Multiplexing Access (CDMA) systems is presented. In the proposed scheme, by applying the new spatial structure lot the receiver, the system can debate the problem of which the number of users exceeds the number of adaptive antenna elements existing in the conventional spatial scheme. An adaptive algorithm based on the Mean Square Error (MSE) criterion is also derived to update the weight matrix of the proposed scheme. The results of the system capacity enhancement can be achieved by using the proposed approach. Numerical simulations are included fer illustration and verification.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2013.10a
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• pp.103-108
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• 2013

This paper describes basic properties tests and non-rotating dynamic test for rotor blade, flexbeam, and torque tube of which bearingless rotor in helicopter consists. A basic properties test are bending and twist test to find the flap stiffness, lag stiffness, and twist stiffness of specimens. The purpose of dynamic test is to find natural frequencies and modes in non-rotating state. The test results are used to update the analysis model. The updated analysis results using rotorcraft comprehensive code match the tests quite well. The updated model input based on the tests will be utilized to analysis the conditions of rotating whirl tower test before the whirl test and will be compared with the whirl tower test results.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.1892-1897
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• 2012

In this paper, efficient CNU(Check Node Update) algorithms are analyzed for high speed LDPC decoding in DVB-S2 standard. In aspect to CNU methods, there are some kinds of CNU methods. Among of them, MP (Min Product) method is quite often used in LDPC decoding. However MP needs LUT (Look Up Table) that is critical path in LDPC decoding speed. A new SC-NMS (Self-Corrected Normalized Min-Sum) method is proposed in the paper. NMS needs only normalized scaling factor instead of LUT and compensates the overestimation of MP approximation. In addition, SC method is proposed. It gives a faster convergence toward a decoded codeword. If a message change its sign between two iterations, it is not reliable and to avoid to propagate noisy information, its module is set to 0. The performance of SC-NMS has a little degrade compare to MP by 0.1 dB, however considering computational complexity and decoding speed, SC-NMS algorithm is optimal method for CNU algorithm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.10 s.101
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• pp.965-972
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• 2005

In this paper, we first review LDPC codes in general and a belief propagation algorithm that works in logarithm domain. LDPC codes, which is chosen for second generation digital video broadcasting standard, are required a large number of computation due to large size of coded block and iteration. Therefore, we presented two kinds of low computational algorithm for LDPC codes. First, sequential decoding with partial group is proposed. It has same H/W complexity, and fewer number of iteration's are required at same performance in comparison with conventional decoder algerian. Secondly, early detection method for reducing the computational complexity is proposed. Using a confidence criterion, some bit nodes and check node edges are detected early on during decoding. Through the simulation, we knew that the iteration number are reduced by half using subset algorithm and computational complexity of early detected method is about $50\%$ offs in case of check node update, $99\%$ offs in case of check node update compared to conventional scheme.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2C
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• pp.148-154
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• 2010

In this paper, we first review LDPC codes in general and a belief propagation algorithm that works in logarithm domain. LDPC codes, which is chosen 802.11n for wireless local access network(WLAN) standard are required a large number of computation due to large size of coded block and iteration. Therefore, we presented three kinds of low computational algorithm for LDPC codes. First, sequential decoding with partial group is proposed. It has same H/W complexity, and fewer number of iteration's are required at same performance in comparison with conventional decoder algorithm. Secondly, we have apply early stop algorithm. This method is reduced number of unnecessary iteration. Third, early detection method for reducing the computational complexity is proposed. Using a confidence criterion, some bit nodes and check node edges are detected early on during decoding. Through the simulation, we knew that the iteration number are reduced by half using subset algorithm and early stop algorithm is reduced more than one iteration and computational complexity of early detected method is about 30% offs in case of check node update, 94% offs in case of check node update compared to conventional scheme.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.5
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• pp.596-603
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• 2019

A reprogramming operation is necessary to update the software code of the node to change or update the functionality of the deployed node in wireless sensor networks. This paper proposes an optimization algorithm that minimizes the transmission energy of a node for the purpose of reprogramming a node in wireless sensor networks. We also design an algorithm that keeps energy consumption of all nodes balanced in order to maintain the lifetime of the network. In this paper, we propose a Tabu search algorithm with a new neighborhood generation method for minimizing transmission energy and energy consumption in wireless sensor networks with many nodes. The proposed algorithm is designed to obtain optimal results within a reasonable execution time. The performance of the proposed Tabu search algorithm was evaluated in terms of the node's transmission energy, remaining energy, and algorithm execution time. The performance evaluation results showed better performance than the previous methods.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.16 no.2
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• pp.658-675
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• 2022

This paper presents a fast-simplified successive cancellation (SC) flipping (Fast-SSC-Flip) decoding algorithm for polar code. Firstly, by researching the probability distribution of the number of error bits in a node caused by channel noise in simplified-SC (SSC) decoder, a measurement criterion of node reliability is proposed. Under the guidance of the criterion, the most unreliable nodes are firstly located, then the unreliable bits are selected for flipping, so as to realize Fast-SSC-Flip decoding algorithm based on node reliability (NR-Fast-SSC-Flip). Secondly, we extended the proposed NR-Fast-SSC-Flip to multiple node (NR-Fast-SSC-Flip-ω) by considering dynamic update to measure node reliability, where ω is the order of flip-nodes set. The extended algorithm can correct the error bits in multiple nodes, and get good performance at medium and high signal-to-noise (SNR) region. Simulation results show that the proposed NR-Fast-SSC-Flip decoder can obtain 0.27dB and 0.17dB gains, respectively, compared with the traditional Fast-SSC-Flip [14] and the newly proposed two-bit-flipping Fast-SSC (Fast-SSC-2Flip-E2) [18] under the same conditions. Compared with the newly proposed partitioned Fast-SSC-Flip (PA-Fast-SSC-Flip) (s=4) [18], the proposed NR-Fast-SSC-Flip-ω (ω=2) decoder can obtain about 0.21dB gain, and the FER performance exceeds the cyclic-redundancy-check (CRC) aided SC-list (CRC-SCL) decoder (L=4).

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.105-113
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• 2013

RAID systems have been widely used by connecting several disks in parallel structure. to resolve the delay and bottleneck of data I/O. Recently, SSD based RAID systems are emerging since SSDs have better I/O performance than HDD. However, endurance and power consumption problems due to frequent write operation in SSD based RAID system should be resolved. In this paper, we propose a de-duplication method of parity disk in SSD based RAID system with expensive update cost. The proposed method segments chunk of parity data into small pieces and removes duplicate data, therefore, it can reduce wear-leveling and power consumption by decreasing write operation for duplicated parity data. Experimental results show that bit update rate of the proposed method is 16% in total disk, 31% in parity disk less than that of existing method in RAID-6 system using EVENODD erasure code, and the power consumption of the proposed method is 30% less than that of existing method. Besides the proposed method is 12% in total disk, 32% in parity disk less than that of existing method in RAID-5 system, and the power consumption of the proposed method is 36% less than that of existing method.

• Convergence Security Journal
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• v.4 no.2
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• pp.27-34
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• 2004

The recent explosive use of the Internet and the development of computer communication technologies reveal serious computer security problem. Inspite of many studies on secure access to the system, generally, the attackers do not use the previous intrusion techniques or network flaw, rather they tend to use the vulnerabilities residing inside the program, which are the running programs on the system or the processes for the service. Therefore, the security managers must focus on updating the programs with lots of time and efforts. Developers also need to patch continuously to update the Program, which is a lot of burden for them. In order to solve the problem, we need to understand the vulnerabilities in the program, which has been studied for some time. And also we need to analyze the functions that contains some vulnerabilities inside. In this paper, we first analyzed the vulnerabilities of the standard C library, and Win32 API functions used in various programs. And then we described the design and implementation of the automated scanning tool for writing secure source code based on the analysis.