• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.2
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• pp.409-413
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• 2010

We fabricated 10 nm-thick cobalt silicide($CoSi_2$) as a buffer layer on a p-type Si(100) substrate to investigate the possibility of GaN epitaxial growth on $CoSi_2/Si(100)$ substrates. We deposited 500 nm-GaN on the cobalt silicide buffer layer at low temperature with a PA-MBE (plasma assisted-molecular beam epitaxy) after the $CoSi_2/Si$ substrates were cleaned by HF solution. An optical microscopy, AFM, TEM, and HR-XRD (high resolution X-ray diffractometer) were employed to determine the GaN epitaxy. For the GaN samples without HF cleaning, they showed no GaN epitaxial growth. For the GaN samples with HF cleaning, they showed $4\;{\mu}m$-thick GaN epitaxial growth due to surface etching of the silicide layers. Through XRD $\omega$-scan of GaN <0002> direction, we confirmed the cyrstallinity of GaN epitaxy is $2.7^{\circ}$ which is comparable with that of sapphire substrate. Our result implied that $CoSi_2/Si(100)$ substrate would be a good buffer and substrate for GaN epitaxial growth.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.19 no.4
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• pp.159-164
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• 2009

We fabricated 40 nm-thick cobalt silicide ($CoSi_2$) as a buffer layer, on p-type Si(100) and Si(111) substrates to investigate the possibility of GaN epitaxial growth on $CoSi_2$/Si substrates. We deposited GaN using a HVPE (hydride vapor phase epitaxy) with two processes of process I ($850^{\circ}C$-12 minutes + $1080^{\circ}C$-30 minutes) and process II ($557^{\circ}C$-5 minutes + $900^{\circ}C$-5 minutes) on $CoSi_2$/Si substrates. An optical microscopy, FE-SEM, AFM, and HR-XRD (high resolution X-ray diffractometer) were employed to determine the GaN epitaxy. In case of process I, it showed no GaN epitaxial growth. However, in process II, it showed that GaN epitaxial growth occurred. Especially, in process II, GaN layer showed selfaligned substrate separation from silicon substrate. Through XRD ${\omega}$-scan of GaN <0002> direction, we confirmed that the combination of cobalt silicide and Si(100) as a buffer and HVPE at low temperature (process II) was helpful for GaN epitaxy growth.

• Journal of the Korean institute of surface engineering
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• v.32 no.3
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• pp.389-392
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• 1999

We employed cobalt-disilicide for high-speed logic devices. We prepared stable and low resistant $CoSi_2$ through typical fabrication process including wet cleaning and rapid thermal process (RTP). We sputtered 15nm thick cobalt on the wafer and performed RTP annealing 2 times to obtain 60nm thick $CoSi_2$. We observed spherical shape voids with diameter of 40nm in the surface and inside $CoSi_2$ layers. The voids resulted in taking over abnormal junction leakage current and contact resistance values. We report that the voids in $CoSi_2$ layers are resulted from surface pits during the ion implantation previous to deposit cobalt layer. Silicide reaction rate around pits was enhanced due to Gibbs-Thompson effects and the volume expansion of the silicidation of the flat active regime trapped dimples. We confirmed that keeping the buffer oxide layer during ion implantation and annealing the silicon surface after ion implantation were required to prevent void defects in CoSi$_2$ layers.