• Title/Summary/Keyword: Clock_offset

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A MB-OFDM UWB Receive Design and Evaluation Using 4. Parallel Synchronization Architecture (4 병렬 동기 구조를 이용한 MB-OFDM UWB 수신기 설계 및 평가)

  • Shin Cheol-Ho;Choi Sangsung;Lee Hanho;Pack Jeong-Ki
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.16 no.11 s.102
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    • pp.1075-1085
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    • 2005
  • The purpose of this paper is to design the architecture for synchronization of MB-OFDM UWB system that is being processed the standardization for Alt-PHY of WPAN(Wireless Personal Area Network) at IEEE802.15.3a and to analyze the implementation loss due to 4 parallel synchronization architecture for design or link margin. First an overview of the MB-OFDM UWB system based on IEEE802.15.3a Alt-PHY standard is described. The effects of non-ideal transmission conditions of the MB-OFDM UWB system including carrier frequency offset and sampling clock offset are analyzed to design a full digital architecture for synchronization. The synchronization architecture using 4-parallel structure is then proposed to consider the VLSI implementation including algorithms for carrier frequency offset and sampling clock offset to minimize the effects of synchronization errors. The overall performance degradation due to the proposed synchronization architecture is simulated to be with maximum 3.08 dB of the ideal receiver in maximum carrier frequency offset and sampling clock offset tolerance fir MB-OFDM UWB system.

DETERMINATION OF GPS RECEIVER CLOCK ERRORS USING UNDIFFERENCE PHASE DATA

  • Yeh, Ta-Kang;Chung, Chen-Yu;Chang, Yu-Chung;Luo, Yu-Hsin
    • Proceedings of the KSRS Conference
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    • 2008.10a
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    • pp.277-280
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    • 2008
  • Enhancing the positioning precision is the primary pursuit of GPS users. To achieve this goal, most studies have focused on the relationship between GPS receiver clock errors and GPS positioning precision. This study utilizes undifferentiated phase data to calculate GPS clock errors and to compare with the frequency of cesium clock directly, thus verifying estimated clock errors by the method used in this paper. The relative frequency offsets from this paper and from National Standard Time and Frequency Laboratory of Taiwan match to $1.5{\times}10^{12}$ in the frequency instability, suggesting that the proposed technique has reached a certain level of quality. The built-in quartz clocks in the GPS receivers yield relative frequency offsets that are 3 to 4 orders higher than those of rubidium clocks. The frequency instability of the quartz clocks is on average two orders worse than that of the rubidium clock. Using the rubidium clock instead of the quartz clock, the horizontal and vertical positioning accuracies were improved by 26-78% (0.6-3.6 mm) and 20-34% (1.3-3.0 mm), respectively, for a short baseline. These improvements are 7-25% (0.3-1.7 mm) and 11% (1.7 mm) for a long baseline. Our experiments show that the frequency instability of clock, rather than relative frequency offset, is the governing factor of positioning accuracy.

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Estimation of GPS Holdover Performance with Ladder Algorithm Used for an UFIR Filter (UFIR 필터 Ladder 알고리즘 이용 GPS Holdover 성능 추정)

  • Lee, Young-kyu;Yang, Sung-hoon;Lee, Chang-bok;Heo, Moon-beom
    • Journal of Institute of Control, Robotics and Systems
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    • v.21 no.7
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    • pp.669-676
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    • 2015
  • In this paper, we described the simulation results of the phase offset performance of a clock in holdover mode which was normally operated in GPS Disciplined Oscillator (GPSDO). In the TIE model, we included the time error term caused by environmental temperature variation because one of the most important parameters of clock phase error is the frequency offset and drift caused by the variation of temperature. For the simulation, we employed Maximum Time Interval Error (MTIE) for the performance evaluation when the frequency offset and drift are estimated by using an Unbiased Finite Impulse Response (UFIR) filter with ladder algorithm. We assumed that the noise in the GPS measurement is white Gaussian with zero mean and 1 ns standard deviation, and temperature linearly varies with a slope of $1{^{\circ}C}$ per hour. From the simulation results, the followings were observed. First, with the estimation error of temperature of less than 3 % and the temperature compensation period of less than 900 seconds, the requirement of CDMA2000 phase synchronization under 10 us could be achieved for more than 40,000 seconds holdover time if we employ an OCXO (Oven Controlled Crystal Oscillator) clock. Second, in order to achieve the requirement of LTE-TDD under 1.5 us for more than 10,000 seconds holdover time, below 3 % estimation error and 500 seconds should be retained if a Rubidium clock is adopted.

DETERMINATION OF CLOCK OFFSET USING GPS CARRIER PHASE MEASUREMENTS (GPS 반송파위상 데이터를 이용한 시계오차 추출)

  • Ha, Ji-Hyun;Park, Kwan-Dong;Lee, Chang-Bok
    • Journal of Astronomy and Space Sciences
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    • v.22 no.4
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    • pp.491-500
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    • 2005
  • Every time laboratory in the world follows an international standard time scale and GPS (Global Positioning System) is playing an important role. Korea Research Institute of Standards and Science is also operating a permanent GPS station for time transfer. To improve the accuracy and precision of the clock offsets derived from GPS we used carrier phase measurements. In addition, we tested four different kinds of GPS satellite orbits and compared the results. The precision of the time offsets using rapid and ultra-rapid orbits was about 0.5 nanoseconds (ns). Tn the case of broadcast orbits, the precision was better than 2 ns.

Design of Calibration Circuit for LCOS Microdisplay (LCOS 마이크로디스플레이 구동용 보정회로 설계)

  • Lee, Youn-Sung;Wee, Jung-Wook;Han, Chung-Woo;Song, Nam-Chol
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2022.10a
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    • pp.469-471
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    • 2022
  • This paper presents an implementation of a calibration circuit to correct the gain error, DC offset and sampling clock phase error generated in the process of converting digital pixels to analog pixels to drive an analog-driven 4K UHD LCOS panel. The proposed calibration circuit consists of a gain and DC offset adjustment circuit and a sampling clock phase adjustment circuit. The calibration circuit is implemented with an FPGA device, and video amplifiers.

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System Performance Improvement of IEEE 802.15.3a By Using Time Slot Synchronization In MAC Layer (UWB MAC의 Time Slot 동기를 통한 시스템 성능 개선)

  • Oh Dae-Gun;Chong Jong-Wha
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.43 no.3 s.345
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    • pp.84-94
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    • 2006
  • In this paper, we propose the algorithm to reduce guard time of UWB MAC time slot for throughput gain. In the proposed draft by multiband ofdm alliance (MBOA), Guard time of each medium access slot (MAS) is composed of shortest inter-frame space (SIFS) and MaxDrift which is the time caused by maximum frequency offset among devices. In this paper, to reduceguard time means that we nearly eliminate MaxDrift term from guard time. Each device of a piconet computes relative frequency offset from the device initiating piconet using periodically consecutive transferred beacon frames. Each device add or subtract the calculated relative frequency offset to the estimated each MAS starting point in order to synchronize with calculated MAS starting point of the device initiating piconet. According to verification of simulations, if the frequency offset estimator is implemented with 8 decimal bit, the ratio of the wasted time to Superframe is always less than 0.0001.

Method of Clock Noise Generation Corresponding to Clock Specification

  • Lee, Young Kyu;Yang, Sung Hoon;Lee, Chang Bok;Kim, Sanhae;Song, Kyu-Ha;Lee, Wonjin;Ko, Jae Heon
    • Journal of Positioning, Navigation, and Timing
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    • v.5 no.3
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    • pp.157-163
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    • 2016
  • Clocks for time synchronization using radio signals such as global navigation satellite system (GNSS) may lose reference signals by intentional or unintentional jamming. This is called as holdover. When holdover occurs, a clock goes into free run in which synchronization performance is degraded considerably. In order to maintain the required precise time synchronization during holdover, accurate estimation on main parameters such as frequency offset and frequency drift is needed. It is necessary to implement an optimum filter through various simulation tests by creating clock noise in accordance with given specifications in order to estimate the main parameters accurately. In this paper, a method that creates clock noise in accordance with given specifications is described.

A Wideband Clock Generator Design using Improved Automatic Frequency Calibration Circuit (개선된 자동 주파수 보정회로를 이용한 광대역 클록 발생기 설계)

  • Jeong, Sang-Hun;Yoo, Nam-Hee;Cho, Seong-Ik
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.60 no.2
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    • pp.451-454
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    • 2011
  • In this paper, a wideband clock generator using novel Automatic frequency calibration(AFC) scheme is proposed. Wideband clock generator using AFC has the advantage of small VCO gain and wide frequency band. The conventional AFC compares whether the feedback frequency is faster or slower then the reference frequency. However, the proposed AFC can detect frequency difference between reference frequency with feedback frequency. So it can be reduced an operation time than conventional methods AFC. Conventional AFC goes to the initial code if the frequency step changed. This AFC, on the other hand, can a prior state code so it can approach a fast operation. In simulation results, the proposed clock generator is designed for DisplayPort using the CMOS ring-VCO. The VCO tuning range is 350MHz, and a VCO frequency is 270MHz. The lock time of clock generator is less then 3us at input reference frequency, 67.5MHz. The phase noise is -109dBC/Hz at 1MHz offset from the center frequency. and power consumption is 10.1mW at 1.8V supply and layout area is $0.384mm^2$.

A Survey of Time Synchronization Techniques in Underwater Acoustic Networks (수중 음향 네트워크를 위한 시간 동기화 기술 동향 분석에 대한 연구)

  • Cho, A-Ra;Yun, Changho;Lim, Yong-Kon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.39C no.3
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    • pp.264-274
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    • 2014
  • Time synchronization becomes a critical issue in underwater acoustic networks (UANets) because nodes cooperate together or individually work by communicating each other in diverse underwater applications. Compared with the time synchronization approaches in terrestrial networks, several intrinsic limitations of UANets (e.g., the unavailability of GPS, long propagation delay, mobility due to currents, limited energy consumption, or low data rate) need to be considered in synchronizing the timing among underwater nodes. For the purpose of developing more efficient time synchronization protocols for UANets, we review the existing approaches, which estimate both the clock offset and the clock skew of underwater nodes. Finally, we outline the state-of-the art time synchronization protocols for UANets by comparing and summarizing them according to their synchronization characteristics.

Ranging Enhancement using Frequency Offset Compensation in High Rate UWB (고속 UWB에서 주파수 편이 보상을 사용한 거리추정 성능향상)

  • Nam, Yoon-Seok;Jang, Ik-Hyeon
    • The KIPS Transactions:PartC
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    • v.16C no.2
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    • pp.229-236
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    • 2009
  • UWB signal with high resolution capability can be used to estimate ranging and positioning in wireless personal area networks. The clock frequency differences of nodes have serious affects on asynchronous ranging methods to estimate locations of mobile nodes. The specification of high rate UWB describes successive TWR method with the estimation of a relative clock frequency offset. In this paper, we complete the ranging equations using relative frequency offset and time information, and propose a method to estimate the exact frequency offsets. We evaluate the ranging algorithms with simulation. The results show that the performances of the algorithms using frequency offsets are very close without noise. But, at noise environment, the method of exact frequency offsets shows better performance than that of relative frequency offsets.