• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.4
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• pp.303-309
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• 2013

A low power 6-bit flash ADC that uses an input voltage range detection algorithm is described. An input voltage level detector circuit has been designed to overcome the disadvantages of the flash ADC which consume most of the dynamic power dissipation due to comparators array. In this work, four digital input voltage range detectors are employed and each input voltage range detector generates the specific clock signal only if the input voltage falls between two adjacent reference voltages applied to the detector. The specific clock signal generated by the detector is applied to turn the corresponding latched comparators on and the rest of the comparators off. This ADC consumes 68.82mW with a single power supply of 1.2V and achieves 4.9 effective number of bits for input frequency up to 1MHz at 500 MS/s. Therefore it results in 4.75pJ/step of Figure of Merit (FoM). The chip is fabricated in 0.13-um CMOS process.

• Journal of Preventive Medicine and Public Health
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• v.13 no.1
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• pp.27-34
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• 1980

Purpose of this study is to find out proper means of estimating the urinary mercury excretion in the normal individuals. Whole void volume was collected every 2 hours beginning from 6 o'clock in the morning until 6 o'clock next morning. Mercury excretion in each urine specimen was measured by NIOSH recommended dithizone colorimetric method (Method No.: P & CAM 145). Urinary concentration of mercury was adjusted by two means: specific gravity of 1.024 and a gram of creatinine excretion per liter of urine comparing the data with the unadjusted ones. Mercury excretion in 24-hour urine specimen was calculated by adding the amounts measured with the hourly collected specimens of each individual. Statistical analysis of the urinary mercury excretion revealed the following results: 1. Frequency distribution curve of mercury excreted in urine of hourly specimens was best fitted to power function expressed in the form of $y=ax^b$. Adjustment of the urinary mercury concentration by creatinine excretion was shown to be superior($y=1674x^{-1.52},\;r^2=0.95$) over nonadjustment($y=2702x^{-1.57},\;r^2=0.92$) and adjustment by specific gravity of 1.024($y=4535x^{-1.66},\;r^2=0.93$). 2. Both log-transformed mercury excretion in hourly voided specimens and mercury excretion itself in 24 hour specimens showed the normal distributions. 3. The frequency distribution of mercury adjusting the urinary concentration of mercury by creatinine excretion was best fitted to a theoretical normal distribution with the sample means and standard deviation than those unadjusted or adjusted with specific gravity of 1.024. 4. Average urinary mercury excretions in 24-hour urine specimen in an individual were as follows: a) Unadjusted mercury excretion mean and standard deviation : $$18.6{\pm}13.68{\mu}gHg/l$$. median : $$16.0\;{\mu}gHg/l$$. range : $$0.0-55.10\;{\mu}gHg/l$$. b) Adjusted with specific gravity mean : $$20.7{\pm}11.76\;{\mu}gHg/l{\times}\frac{0.024}{S.G-1.000}$$ median : $$20.7\;{\mu}gHg/l{\times}\frac{0.024}{S.G-1.000}$$ range : $$0.0-52.9\;{\mu}gHg/l{\times}\frac{0.024}{S.G-1.000}$$ c) Adjusted with creatinine excretion mean and standard deviation : $$10.5{\pm}6.98\;{\mu}gHg/g$$ creatinine/l median : $$9.4\;{\mu}gHg/g$$ creatinine/l range : $$0.0-26.7\;{\mu}gHg/g$$ creatinine/l 5. No statistically significant differences were found between means calculated from 24-hour urine specimens and those from hourly specimens transformed into logarithmic values. (P<0.05).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.2
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• pp.237-241
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• 2005

In Bluetooth version 1.0, the frequency hopping algorithm was such that there was one piconet, using a specific frequency, resolving the frequency depending on the part of the digits of the device clock and the Bluetooth address. Basic pattern was a kind of a round-robin using 79 frequencies in the ISM band. At this point, a problem occurs if there were more than two devices using the same frequency within specific range. In this paper, we proposed a software-based adaptive frequency hopping method so that more than two wireless devices can stay connected without frequency crash. Suggested method was implemented with HDL(Hardware Description Language) and automatically synthesized and laid out. Implemented adaptive frequency hopping circuit operated well in 24MHz correctly.

• ETRI Journal
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• v.30 no.1
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• pp.129-140
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• 2008

In this paper, we propose a novel ant colony optimization (ACO)-based test scheduling method for testing network-on-chip (NoC)-based systems-on-chip (SoCs), on the assumption that the test platform, including specific methods and configurations such as test packet routing, generation, and absorption, is installed. The ACO metaheuristic model, inspired by the ant's foraging behavior, can autonomously find better results by exploring more solution space. The proposed method efficiently combines the rectangle packing method with ACO and improves the scheduling results by dynamically choosing the test-access-mechanism widths for cores and changing the testing orders. The power dissipation and variable test clock mode are also considered. Experimental results using ITC'02 benchmark circuits show that the proposed algorithm can efficiently reduce overall test time. Moreover, the computation time of the algorithm is less than a few seconds in most cases.

• Journal of Institute of Control, Robotics and Systems
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• v.6 no.2
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• pp.228-233
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• 2000

It is common to apply the technology of FPGA (Fie이 Programmable Gate Array) which is one of the design methods for ASIC(Application Specific IC)to the active components used in the data processing at the digital system of satellite aircraft missile etc for compact lightness and integration of Printed Circuit Board (PCB) In carrying out the digital data processing the FPGAs are designed for the various functions of the Process Control Interrupt Control Clock Generation Error Detection and Correction (EDAC) as the individual module. In this paper an FPGA chip for Single Error Correction and Double Error Detection (SEC-DED) for EDAC is designed and simulated by using a VLSI design software LODECAP.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2000.11b
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• pp.95-100
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• 2000

본 논문에서는 디지털 TV 방송 스트림을 분석, 검증하기 위한 시스템을 PC 상에서 소프트웨어 기반으로 구현하였다. 저장되어 있는 MPEG-2 트란스포트 스트림(transport stream, TS) 파일을 입력으로 받으며 별도의 하드웨어 장치를 사용하지 않는다. 이 분석기는 PSI(program specific information), TS 섹션, TS 헤더 등 기본 내용뿐만 아니라, TS 패킷들을 오디오, 비디오, PCR(program clock reference), 부가 데이터, 널(null) 패킷 등으로 구분하여 그래픽 사용자 인터페이스 통하여 보여 준다. 또한, 현재 표시되고 있는 TS 패킷과 가장 가까운 I 프레임를 디스플레이 해줌으로써 비트스트림 상의 오류 부분과 실제 영상과 쉽게 매칭시킬 수 있도록 해 준다. 본 논문의 분석기는 MPEG-2 비트스트림 적합성 검사 기능도 제공하며, 데이터 방송을 위한 여러 가지 부가 데이터를 MPEG-2 기본 스트림에 삽입하는 기능도 갖고 있다. 본 논문의 분석기를 이용함으로써 저비용으로 방송 스트림을 분석, 검증할 수 있을 뿐만 아니라, 실험실 연구를 위한 데이터 방송용 비트스트림을 저비용으로 제작할 수 있다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.1C
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• pp.80-86
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• 2006

In this paper, we propose the PingPong-128(PP-128) keystream generator, based on summation generator. Proposed PingPong-128, a specific cipher of the PingPong Family, takes 128 bits key and 128 bit initial vector, has 258 bit internal state, and achieves a security level of 128 bits. The security analysis of PingPong-128 is presented, including the resistence to known attacks against the summation generator and other clock-controlled generators.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.144-147
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• 2000

Data security is an important issue in today's computer networks. In order to construct a safe infra in the open communication network, a cryptography is necessarily applied to several communication application fields like a high-speed networking system supporting real-time operation. A cryptography which has already realized by a software is designed by using a hardware to improve a throughput. In this paper, we design hardware architecture of IDEA by using a single iterative round method to improve a encryption throughput. In addition, we intend to develop a hardware design methodology that a specific cryptography operate with high-speed. The hardware model is described in VHDL and synthesized by the Samsung KG 80 Library in the Synopsys development software tool. With a system clock frequency 20MHz, this hardware permits a data conversion rate of more than 116 Mbit/s.

• Journal of information and communication convergence engineering
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• v.7 no.3
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• pp.399-403
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• 2009

In IEEE 802.15.1 (Bluetooth) Ad-hoc networks, the frequency is resolved by the specific part of the digits of the Device clock and the Bluetooth address of the Master device in a given piconet. The piconet performs a fast frequency hopping scheme over 79 carriers of 1-MHz bandwidth. Since there is no coordination between different piconets, packet collisions may occur if two piconets are located near one another. In this paper, we proposed a software/hardware co-design of an adaptive frequency decision mechanism so that more than two different kinds of wireless devices can stay connected without frequency collision. Suggested method was implemented with C program and HDL (Hardware Description Language) and automatically synthesized and laid out. The adaptive frequency hopping circuit was implemented in a prototype and showed its operation at 24MHz correctly.

• Journal of the Korea Society for Simulation
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• v.7 no.1
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• pp.15-26
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• 1998

In building a shell-based FMS, which is known as one of the top-down approaches in the field of factory automation, we may take a hybrid simulation into consideration. The modeling of a hybrid simulation consists of real physical entities, virtual simulation, and central clock algorithm, etc. to carry out the whole system operation. In this paper, we sow a way to construct a hybrid simulation software system in manufacturing environments. We bring in the object-oriented methodology in system design and it can contribute in dealing with a wide variety of production types and configurations. Some classes such as project, product, process, order, schedule, stage are defined. These are used and tested by implementing a specific LSI circuit assembly line process.