• Title/Summary/Keyword: Clamping Diode

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Analysis and Implementation of LC Series Resonant Converter with Secondary Side Clamp Diodes under DCM Operation for High Step-Up Applications

  • Jia, Pengyu;Yuan, Yiqin
    • Journal of Power Electronics
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    • v.19 no.2
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    • pp.363-379
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    • 2019
  • Resonant converters have attracted a lot of attention because of their high efficiency due to the soft-switching performance. An isolated high step-up converter with secondary-side resonant loops is proposed and analyzed in this paper. By placing the resonant loops on the secondary side, the current stress for the resonant capacitors is greatly reduced. The power loss caused by the equivalent series resistance of the resonant capacitor is also decreased. Clamp diodes in parallel with the resonant capacitors ensure a unique discontinuous current mode in the converter. Under this mode, the active switches can realize soft-switching during both turn-on and turn-off transitions. Meanwhile, the reverse-recovery problems of diodes are also alleviated by the leakage inductor. The converter is essentially a step-up converter. Therefore, it is helpful for decreasing the transformer turn-ratio when it is applied as a high step-up converter. The steady-state operation principle is analyzed in detail and design considerations are presented in this paper. Theoretical conclusions are verified by experimental results obtained from a 500W prototype with a 35V-42V input and a 400V output.

Development on New Laser Tabbing Process for Modulation of Thin Solar Cell (박형 태양 전지 모듈화를 위한 레이져 태빙 자동화 공정(장비) 개발)

  • No, Donghun;Choi, Chul-June;Cho, Hyun Young;Yu, Jae Min;Kim, JungKeun
    • 한국신재생에너지학회:학술대회논문집
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    • 2010.06a
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    • pp.58.1-58.1
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    • 2010
  • In solar cell module manufacturing, single solar cells has to be joined electrically to strings. Copper stripes coated with tin-silver-copper alloy are joined on screen printed silver of solar cells which is called busbar. The bus bar collects the electrons generated in solar cell and it is connected to the next cell in the conventional module manufacturing by a metal stringer using conventional hot air or infrared lamp soldering systems. For thin solar cells, both soldering methods have disadvantages, which heats up the whole cell to high temperatures. Because of the different thermal expansion coefficient, mechanical stresses are induced in the solar cell. Recently, the trend of solar cell is toward thinner thickness below 180um and thus the risk of breakage of solar cells is increasing. This has led to the demand for new joining processes with high productivity and reduced error rates. In our project, we have developed a new method to solder solar cells with a laser heating source. The soldering process using diode laser with wavelength of 980nm was examined. The diode laser used has a maximum power of 60W and a scanner system is used to solder dimension of 6" solar cell and the beam travel speed is optimized. For clamping copper stripe to solar cell, zirconia(ZrO)coated iron pin-spring system is used to clamp both joining parts during a scanner system is traveled. The hot plate temperature that solar cell is positioned during lasersoldering process is optimized. Also, conventional solder joints after $180^{\circ}C$ peel tests are compared to the laser soldering methods. Microstructures in welded zone shows that the diffusion zone between solar cell and metal stripes is better formed than inIR soldering method. It is analyzed that the laser solder joints show no damages to the silicon wafer and no cracks beneath the contact. Peel strength between 4N and 5N are measured, with much shorter joining time than IR solder joints and it is shown that the use of laser soldering reduced the degree of bending of solar cell much less than IR soldering.

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Alignment System Development for producing OLED using Fourth-Generation Substrate

  • Park, Jae-Yong;Han, Seok-Yoon;Lee, Nam-Hoon;Choi, Jeong-Og;Shin, Ho-Seon
    • 한국정보디스플레이학회:학술대회논문집
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    • 2008.10a
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    • pp.873-878
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    • 2008
  • Doosan Mecatec has developed alignment system for Organic Light-Emitting Diode (OLED) display production using large size substrate. In the present article, The alignment system between the substrate and the mask, which is a core technology for producing the OLED product using the fourth-generation substrate with $730{\times}920mm^2$ or more, will be described by dividing into a substrate loader, a magnet unit, a CCD camera, etc. The substrate loader is optimized through the simulation where the central portion of the substrate droops by about 1.5mm by clamping each of a long side (920mm direction) and a short side (730mm direction) thereof by 6 point and 4 point. A magnet unit using a sheet type of rubber magnet is constituted and a CCD camera model with the specifications capable of minimizing the errors between a clear image and the same image is selected. The system to which an upward evaporation technique of small molecular organic materials will be applied has been developed so that repeatability and position accuracy becomes ${\pm}1{\mu}m$ or less using an UVW type of stage. Also, the vision accuracy of the CCD camera becomes ${\pm}1{\mu}m$ or less and the align process TACT becomes 30sec. or less so that the final alignment accuracy between the substrate and the mask becomes ${\pm}3{\mu}m$ or less. In order to meet an extra-large glass substrate, an evaporation system using an extra-large AMOLED substrate has been developing through a vertical type of an alignment system.

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A $64\times64$ IRFPA CMOS Readout IC for Uncooled Thermal Imaging (비냉각 열상장비용 $64\times64$ IRFPA CMOS Readout IC)

  • 우회구;신경욱;송성해;박재우;윤동한;이상돈;윤태준;강대석;한석룡
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.36C no.5
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    • pp.27-37
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    • 1999
  • A CMOS ReadOut Integrated Circuit (ROlC) for InfraRed Focal Plane Array (IRFPA) detector is presented, which is a key component in uncooled thermal imaging systems. The ROIC reads out signals from $64\times64$ Barium Strontium Titanate (BST) infrared detector array, then outputs pixel signals sequentially after amplifying and noise filtering. Various design requirements and constraints have been considered including impedance matching, low noise, low power dissipation and small detector pitch. For impedance matching between detector and pre~amplifier, a new circuit based on MOS diode structure is devised, which can be easily implemented using standard CMOS process. Also, tunable low pass filter with single~pole is used to suppress high frequency noise. In additions, a clamping circuit is adopted to enhance the signal~to-noise ratio of the readout output signals. The $64\times64$ IRFPA ROIC is designed using $0.65-\mu\textrm{m}$ 2P3M (double poly, tripple metal) N~Well CMOS process. The core part of the chip contains 62,000 devices including transistors, capacitors and resistors on an area of about $6.3-mm\times6.7-mm$.

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