• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.2
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• pp.1-6
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• 2002

In this paper, an Analog Flat Panel interface(AFPI) which supports for UXGa(Ultar extended Graphics Array)-Compatible TFT LCD Driver is designed. The Proposed AFPI is composed of 8-b ADC, Automatic Gain Control(AGC), Low-Jitter PLL. In order to obtain a high speed and low power consumption, an efficient architecture of 8-bit ADC is proposed, whose FR(Folding Rate) is 8, NFB(Number of Folding Block) is 2, and IR (Interpolating Rate) is 16. We can get high SNDR by adopting distributed track and hold circuits. Also a programmable AGC which is possible to control gain and clamp, and a low-jitter PLL are proposed. The chip has been fabricated with 0.25${\mu}{\textrm}{m}$ 1-poly S-metal n-well CMOS technology. The effective chip area is 3.6mm $\times$ 3.2mm and it dissipates about 602㎽ at 2.5V power supply. The INL and DNL are within $\pm$ 1LSB. The measured SNDR is about 43㏈, when the input frequency is 10MHz at 200MHz clock frequency.

• Journal of the Korean Society for Precision Engineering
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• v.28 no.6
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• pp.716-723
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• 2011

The battery capacity of electric/hybrid vehicle is much larger than present automobile. For that reason, the connector of Green Car should be designed to transmit the high-electric voltage. In addition, the electromagnetic wave should be shielded to protect communication and signal circuits. In this study, shielding performance of the connector was analyzed through electromagnetic shield analysis, and a connector of Green Car was designed using thermoelectrical analysis, which is capable of transmitting the high-electric power. In the design of connector structure, the improved stability and workability was considered.

• Journal of Electrical Engineering and Technology
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• v.9 no.4
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• pp.1296-1308
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• 2014

This paper presents a new zero voltage switching (ZVS) converter for medium power and high input voltage applications. Three three-level pulse-width modulation (PWM) circuits with the same power switches are adopted to clamp the voltage stress of MOSFETs at $V_{in}/2$ and to achieve load current sharing. Thus, the current stresses and power ratings of transformers and power semiconductors at the secondary side are reduced. The resonant inductance and resonant capacitance are resonant at the transition interval such that active switches are turned on at ZVS within a wide range of input voltage and load condition. The series-connected transformers are adopted in each three-level circuit. Each transformer can work as an inductor to smooth the output current or a transformer to achieve the electric isolation and power transfer. Thus, no output inductor is needed at the secondary side. Three center-tapped rectifiers connected in parallel are used at the secondary side to achieve load current sharing. Compared with the conventional parallel three-level converters, the proposed converter has less switch counts. Finally, experiments based on a 1.44kW prototype are provided to verify the operation principle of proposed converter.