• ETRI Journal
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• 제35권3호
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• pp.431-438
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• 2013

This paper presents a new realization of the implicit root-mean-square (RMS) detector, employing three second-generation current conveyors and MOS transistors. The proposed circuit can be applied in measuring the RMS value of complex, periodic signals, represented in the form of the Fourier series. To verify the theoretical analysis, circuit Simulation Program with Integrated Circuit Emphasis simulations and experiment results are included, showing agreement with the theory.

• 한국시뮬레이션학회:학술대회논문집
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• 한국시뮬레이션학회 1999년도 추계학술대회 논문집
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• pp.272-277
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• 1999

The necessity of voice recording device was increased using voice signal IC with designed LSI/VLSI. The control unit which developed here voice recorder has low power dissipation, portable, and comfortable using voice source. However, the Korea voice recorder abilities far behind of foreign products for its performance and size on sailing. So we used Chua circuit to improvement voice quality abilities after minimize power supply device and circuit by designing voice recording device into lower power dissipation power circuit.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2001년도 ICCAS
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• pp.108.6-108
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• 2001

The basic circuit block diagram of CMOS current mode sum and subtract circuit is present in this paper. The purpose circuit consists of the invert current circuit and the basic current mirror. The outputs of the circuit are the summing of the both input current [lx+ly] and also the subtract of the both input current [lx+(-ly)]. The SPICE simulation results of the electrical characteristics with level 7 (BSIM3 model version 3.1) MOSFET transistor model of the circuit such as the input dynamic range, the frequency response and some system application have been shown and analyzed.

• 한국초전도ㆍ저온공학회논문지
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• 제5권1호
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• pp.44-47
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• 2003

There are several simulation programs in studying superconductor RSFQ (Rapid Single flux Quantum) electronic devices, which include WRspice, WinS, PSCAN, and JSIM. Even though different research groups use different simulation programs, it is not well known about which program gives the simulation results closer to the measurement values. In this work, we used both WRspice and WinS to simulate RSFQ OR gate and to compare the results from the different simulations. This comparison would help in deciding which program is better in the RSFQ circuit design. In the confluence buffer, which is the one of the main components of the DR gate, the measured bias margins were ${\times}23.2%$, while the margins from the simulations were ${\pm}35.56%$ from WRspice and it 53.1% from WinS. However, with the actual fabricated circuit parameters WRspice gave ${\pm}27%$. In WinS the circuit did not operate. We concluded that WRspice is more reliable.

• 전자공학회논문지A
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• 제33A권5호
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• pp.180-187
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• 1996

This paper describes a post-layout simulation method using VHDL and C for verifying the architecture of antifuse-based FPGAs and the dedicated CAD system. An antifuse-based FPGA consists of programming circuitry including decoding logic, logic modules, segmented tracks, antifuses and I/O pads. The VHDL model which includes all these elements is used for logic verification and programming verification of the implemented circuit by reconstructing the logic circuit from the bit-stream generated from layout tool. The implemented circuit comprises of logic modules and routing networks. Since the routing delay of the complex networks is comparable to the delay of the logic module in the FPGA, the accurate post-layout simulation is essential to the FPGA system. In this paper, the C program calculates the delay of the routing netowrks using SPICE, elmore or horowitz delay models and the results feedback to the VHDL simulation. Critical path anc be found from this post-layout simulation results.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권1호
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• pp.49-54
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• 2010

This paper describes a fast circuit simulation technique using the latency insertion method (LIM) with a parallel and distributed leapfrog algorithm. The numerical simulation results on the PC cluster system that uses the cloud computing system are shown. As a result, it is confirmed that our method is very useful and practical.

• Journal of information and communication convergence engineering
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• 제19권4호
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• pp.263-268
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• 2021

Although the compact capacitance model of point tunneling types of tunneling field-effect transistors (TFET) has been proposed, those of line tunneling types of TFETs have not been reported. In this study, a compact capacitance model of an L-shaped TFET (LTFET), a line tunneling type of TFET, is proposed using the previously developed surface potentials and current models of P- and L-type LTFETs. The Verilog-A LTFET model for simulation program with integrated circuit emphasis (SPICE) was also developed to verify the validation of the compact LTFET model including the capacitance model. The SPICE simulation results using the Verilog-A LTFET were compared to those obtained using a technology computer-aided-design (TCAD) device simulator. The current-voltage characteristics and capacitance-voltage characteristics of N and P-LTFETs were consistent for all operational bias. The voltage transfer characteristics and transient response of the inverter circuit comprising N and P-LTFETs in series were verified with the TCAD mixed-mode simulation results.

• 반도체디스플레이기술학회지
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• 제20권4호
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• pp.141-145
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• 2021

The brightness of the Organic Light Emitting Diode (OLED) display is controlled by thin-film transistors (TFTs). Regardless of the materials and the structures of TFTs, an OLED suffers from the instable threshold voltage (V_th) of a TFT during operation. When designing an OLED pixel with circuit simulation tool such as SPICE, a designer needs to take V_th shift into account to improve the reliability of the circuit and various compensation methods have been proposed. In this paper, the effect of the compensation circuits from two typical OLED pixel circuits proposed in the literature are studied by the transient simulation with a SPICE tool in which the stretched-exponential time dependent V_th shift function is implemented. The simulation results show that the compensation circuits improve the reliability at the beginning of each frame, but V_th shifts from all TFTs in a pixel need to be considered to improve long-time reliability.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.803-806
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• 1998

A novel bipolar circuit technique for realizing linear transconductor is described. The proposed circuit has superior linearity and temperature characteristics when compared with the conventional transconductor. The theory of operation is presented and computer simulation results are used to verify theoretical predections. The simulation results show close agreement between predicted behaviours and experimental performances.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제53권9호
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• pp.576-583
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• 2004

This paper presents a buck circuit topology of high-frequency with a single switching device. It solved the problem which arised from hard-switching in high-frequency using a resonant snubber and operating under the principle of ZCS turn-on and ZVS turn-off commutation schemes. In the existing circuit, it has the voltage stress that is almost twice of input voltage in a free-wheeling diode. In the proposed circuit, it has the voltage stress that is lower than input voltage with modifing a location of free -wheeling diode. In this paper, it expained the circuit operation of each mode and analyzed feedback-loop stabilization. Also it confirmed the waveform of each mode with simulation result. The experiment result verified the simulation waveform and compared the voltage stress of a free -wheeling diode in the exsiting circuit with the voltage stress of that in the proposed circuit. Moreover, it compares and analyzes the proposed circuit's efficiency with the hard-switching circuit's efficiency according to the change of load current.