• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2005년도 제36회 하계학술대회 논문집 C
• /
• pp.2318-2320
• /
• 2005

In this paper, a low noise amplifier(LNA) in a receiver of a Low Noise Block Down Converter (LNB) for direct broadcasting service(DBS) is implemented using GaAs HEMT. The LNA is designed for the bandwidth of 11.7GHz-12.2GHz. The 2stage-LNA consists of a input matching circuit, a output matching circuit, DC-blocks and RF-chokes. The result of a simulation of the LNA using Advanced Design System(ADS) shows the noise figure less than 1.4dB, the gain greater than 23dB and the flatness of 1dB in the bandwidth of 11.7 to 12.2GHz.

• Journal of Semiconductor Engineering
• /
• 제3권1호
• /
• pp.154-160
• /
• 2022

In this paper, we design a DC-DC boost converter with RF noise immunity to supply a stable positive output voltage for OLED displays. For RF noise immunity, an input voltage variation reduction circuit (IVVRC) is adopted to ensure display quality by reducing the undershoot and overshoot of output voltage. The boost converter for a positive voltage Vpos operates in the SPWM-PWM dual mode and has a dead-time controller using a dead-time detector, resulting in increased power efficiency. A chip was fabricated using a 0.18 um BCDMOS process. Measurement results show that power efficiency is 30% ~ 76% for load current range from 1 mA to 100 mA. The boost converter with the IVVRC has an overshoot of 6 mV and undershoot of 4 mV compared to a boost converter without that circuit with 18 mV and 20 mV, respectively.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2001년도 추계학술대회 논문집 Vol.14 No.1
• /
• pp.410-413
• /
• 2001

In this paper, we present results of this that design of the multi-layer VCO(Voltage Controlled Oscillator), which is composed of the resonation circuit and the oscillation circuit, using EM simulator and nonlinear RF circuit simulator. EM simulator is used for acquiring EM(Electromagnetic) characteristics of conductor pattern as well as designing multi-layer VCO, Acquired EM characteristics of the circuit pattern was used like real components at nonlinear RF circuit simulator. Finally VCO is simulated at nonlinear RF circuit simulator. The material for the circuit pattern was Ag and the dielectric was DuPont #9599, which is applied for L TCC process. The structure is constructed with 4 conducting layer. Simulated results showed that the output level was about 1[dBm], the phase noise was 102 [dBc/Hz] at 30[kHz] offset frequency, the harmonics -8dBc, and the control voltage sensitivity of 30[MHz/V] with a DC current consumption of l0[mA]

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2001년도 추계학술대회 논문집
• /
• pp.410-413
• /
• 2001

In this paper, we present results of this that design of the multi-layer VCO(Voltage Controlled Oscillator), which is composed of the resonation circuit and the oscillation circuit, using EM simulator and nonlinear RF circuit simulator. EM simulator is used for acquiring EM(Electromagnetic) characteristics of conductor pattern as well as designing multi-layer VCO, Acquired EM characteristics of the circuit pattern was used like real components at nonlinear RF circuit simulator. Finally VCO is simulated at nonlinear RF circuit simulator. The material for the circuit pattern was Ag and the dielectric was Dupont ＃9599, which is applied for LTCC process. The structure is constructed with 4 conducting layer. Simulated results showed that the output level was about 1[dBm], the phase noise was 102 [dBc/Hz] at 30[kHz] offset frequency, the harmonics -8dBc, and the control voltage sensitivity of 30[MHz/V] with a DC current consumption of 10[mA].

• Journal of electromagnetic engineering and science
• /
• 제16권3호
• /
• pp.191-193
• /
• 2016

This paper proposes a voltage-controlled oscillator (VCO) that has broadband turning and low-level of phase noise characteristics. Due to the micro-strip line resonant circuit with a low Q value, which is applied to the broadband tuning range, the depreciated phase noise performance is compensated by restraining the harmonics of the oscillating frequency. The VCO was designed according to the proposed structure as well as the conventional structure, and the superiority of the proposed structure was verified through its simulation, fabrication, and measurement.

• 한국정보통신설비학회:학술대회논문집
• /
• 한국정보통신설비학회 2007년도 학술대회
• /
• pp.3-6
• /
• 2007

In this paper, a hybrid dual band LNA(Low Noise Amplifier) with a tunable matching circuit using varactor is designed for 433MHz and 912MHz RFID reader. The operating frequency is controlled by the bias voltage applied to the varactor. The measured results demonstrate that S21 parameter is 16.01dB and 10.72dB at 433MHz and 912MHz, respectively with a power consumption of 19.36mW. The S11 are -11.88dB and -3.31dB, the S22 are -11.18dB and -15.02dB at the same frequencies. The measured NF (Noise Figure) is 15.96dB and 7.21dB at 433MHz and 912MHz, respectively. The NF had poorer performance than the simulation results. The reason for this discrepancy was thought that the input matching is not performed exactly and a varactor in the input matching circuit degrades the NF characteristics.

• 한국소음진동공학회:학술대회논문집
• /
• 한국소음진동공학회 1998년도 춘계학술대회논문집; 용평리조트 타워콘도, 21-22 May 1998
• /
• pp.444-449
• /
• 1998

A modal transducer in two-dimensional structure can be implemented by varying the distributed transducer's gain spatially. In this paper, a method based on finite element method is developed for optimizing spatial gain distribution of PVDF transducer to create the modal transducer for specific modes. Using this concept, one can design the modal transducer in two-dimensional structure having arbitrary geometry and boundary conditions. As a practical means for implementing this continuous gain distribution without repoling die PVDF film, the gain distribution is approximated by optimizing gain-weights of interface circuit. The whole spatial area of the PVDF film is divided into several electrode segments and the signals from each segment are properly weighted and summed by interface circuit. This corresponds to the approximation of a continuous function using discrete values. The electrode partition is optimized using the genetic algorithm. Gain-weights are optimized using the simplex search method. A modal sensor for first to fourth modes of aluminum plate is designed using PVDF film with gain-weighted interface circuit. Various lamination angles of PVDF film are taken into consideration to utilize the anisotropy of the PVDF film. Performance of the optimized' PVDF sensor is demonstrated by numerical simulations..

• 전력전자학회논문지
• /
• 제12권5호
• /
• pp.386-393
• /
• 2007

본 논문에서는 CIM(Current Injection Method)을 이용한 charge-pump방식의 plasma backlight용 고압 inverter회로를 제안한다. 고압 inverter에서 에너지 회수회로의 채용은 새로운 시도로서 에너지회수 이외에도 noise에 의한 시스템의 불안정성과 방전안정화에 기여하고 있다. charge-pump방식으로 스위치류의 내압을 저감하므로 cost면에서 매우 유리한 조건을 확립하였으며 CIM(Current Injection Method)방식의 적용으로 high speed 에너지 회수를 가능하게 하였다. 그리고 제안회로의 동작을 모드별로 해석하였으며, 실제 32" 패널에 적용하여 실험함으로써 제안한 회로의 유용성을 입증하였다.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2008년도 제39회 하계학술대회
• /
• pp.942-943
• /
• 2008

The boost converter is usually used in power factor correction. The dynamic losses of its output diode are produced during the reverse recovery time. The power efficiency is decreased due to the losses and also it generates the noise. These disadvantages have been remarkably improved by ZCS and ZVS techniques of power factor improvement circuit. Some benefits lead to the achievement of higher power density and the development cost can be decreased. In this paper work, the reverse recovery suppression(RS) PFC method is used. A inductor and a diode are added into the conventional circuit. The switching device, MOSFET is turned off after the reverse recovery current has come to the zero level. The Zero Current Switching(ZCS) is implemented at that time. This power conversion technique improves the efficiency to about 1% and reduces the noise obviously. And the additional inductor can be designed using an original filter core in the circuit. The converter size is reduced effectively.

• 한국정보기술학회 영문논문지
• /
• 제10권1호
• /
• pp.37-43
• /
• 2020

This paper presents analysis of passive metal interconnection of the LNA block in CMOS integrated circuit. The performance of circuit is affected by the geometry of RF signal path. To investigate the effect of interconnection lines, a cascode LNA is designed, and circuit simulations with full-wave electromagnetic (EM) simulations are executed for different positions of a component. As the results, the position of an external capacitor (C_ex) changes the parasitic capacitance of electric coupling; the placement of component affects the circuit performance. This analysis of interconnection line is helpful to analyze the amount of electromagnetic coupling between the lines, and useful to choose the signal path in the layout design. The target of this work is the RF LNA enabling the seamless connection of wireless data network and the following standards have to be supported in multi-band (WCDMA: 2.11~ 2.17 GHz, CDMA200 1x : 1.84~1.87 GHz, WiBro : 2.3~2.4GHz) mobile application. This work has been simulated and verified by Cadence spectre RF tool and Ansoft HFSS. And also, this work has been implemented in a 0.13um RF CMOS technology process.