• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1989년도 한국자동제어학술회의논문집; Seoul, Korea; 27-28 Oct. 1989
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• pp.7-12
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• 1989

This paper describes the design and development of a PWM electronic controller for a high performance Pneumatic Actuation System. The task includes the design of a closed center valve circuit for minimum gas consumption, the selection of optimum values for key parameters in the PWM circuit, and the design of lag-lead compensation circuit. These were carried out through specific experiments using a prototype pneumatic actuation system. The final performance obtained with the actuation system confirmed the successful design of the developed PWM electronic controller.

• 전자공학회지
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• 제25권5호
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• pp.31-41
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• 1998

With the advent of portable electronic systems, power consumption has recently become a major issue in circuit and system design. Furthermore, the sophisticated fabrication technology makes it possible to embed more functions and features in a VLSI chip, consequently calling for both higher performance and lower power to deal with the ever growing complexity of system algorithms than in the past. VLSI designers should cope with two conflicting constraints, high performance and low power, offering an optimum trade off of these constraints to meet requirements of system. Historically, VLSI designers have focused on performance improvement, and power dissipation was not a design criteria but an afterthought. This design paradigm should be changed, as power is emerging as the most critical design constraint. In VLSI design, low power design can be accomplished through many ways, for instance, process, circuit/logic design, architectural design, and etc.. In this paper, a few low power design examples, which have been used in 8 bit micro-controller core, and can be used also in 4/16/32 bit micro-controller cores, are presented in the areas of circuit, logic and architectural design. We first propose a low power guidelines for micro-controller design in SAMSUNG, and more detailed design examples are followed applying 4 specific design guidelines. The 1st example shows the power reduction through reduction of number of state clocks per instruction. The 2nd example realized the power reduction by applying RISC(Reduced Instruction Set Computer) concept. The 3rd example is to optimize the algorithm for ALU(Arithmetic Logic Unit) to lower the power consumption, Lastly, circuit cells designed for low power are described.

• 전자공학회논문지
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• 제53권12호
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• pp.50-56
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• 2016

이 논문은 UHD 영상을 지원하는 멀티 디코더 용 인트라 예측 회로의 구조와 설계를 제안하고 있다. 제안된 회로는 가장 최신의 비디오 압축 표준인 HEVC뿐만 아니라 H.264도 지원한다. 이 회로는 기본적인 인트라 예측 기능이외에 추가적으로 H.264 표준에 정의되어 있는 참조 샘플 필터 연산과 HEVC 표준에 정의되어 있는 약한 참조 샘플 필터 및 강한 참조 샘플 필터 연산을 처리하는 기능도 갖고 있다. 공통적인 연산부와 내부 저장소를 공유함으로써 회로의 크기를 감소시켰으며, 병렬 연산을 통하여 성능을 향상시켰다. 제안된 회로는 Verilog HDL(Hardware Description Language)을 이용하여 RTL(Register Transfer Level)로 기술하였으며, Cadence의 NC-Verilog를 이용하여 기능을 검증하였다. RTL 회로를 Synopsys의 Design Compiler 및 130nm 표준 셀 라이브러리를 이용하여 합성하였다. 합성된 게이트 수준 회로는 69,694개의 게이트로 구성되며, 최대 동작주파수 157MHz에서 4K-UHD HEVC 영상을 초당 100 ~ 280 프레임의 속도로 처리한다.

• 전기의세계
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• 제22권2호
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• pp.70-74
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• 1973

This paper dealt with circuit modeling of SCR and gate turn-off SCR by using complementary symmetrical tansistor circuit, which is modified circuit of input current dependent, current stable negative resitance circuit. Operation of this circuit is estimated and analyzed, with which compared with conventional SCR modeling circuit. Also operation and the design procedures are checked by experiments.

• 전력전자학회논문지
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• 제13권2호
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• pp.135-144
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• 2008

일반적으로 Intelligent power module (IPM)의 상부 스위치 구동을 위한 플로팅 전원 공급 방법으로 부트스트랩 회로가 많이 사용되고 있다. 부트스트랩 회로는 구성이 간단하고 집적화가 가능하다는 장점이 있으나 몇 가지 문제점을 가지고 있다. 상부 스위치 게이트 드라이버 회로에 전원을 공급하기 위해 매 주기마다 충분한 에너지를 충전할 수 있는 시간이 요구되며, 충전된 에너지는 한정적이므로 스위치 턴 온 (turn-on)시간의 제한을 갖게 된다. 그리고 주파수가 낮아질수록 부트스트랩 커패시터 용량이 증가하여 집적화에 장애요인이 된다. 이러한 단점은 전하 펌프 회로를 사용함으로써 보완될 수 있다. 본 논문에서는 IPM의 플로팅 전원 공급 방법으로 전하 펌프 회로를 적용하여 분석하였으며, 이러한 분석을 기반으로 전하 펌프 회로의 설계 방법을 제안하였다. 분석과 제안된 설계 방법의 타당성을 검증하기 위하여 시뮬레이션과 실험을 수행하였으며, 제시된 결과는 제안된 설계 방법의 유용성을 입증하였다.

• 전력전자학회논문지
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• 제22권4호
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• pp.277-284
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• 2017

For passive power factor correction, the valley fill circuit approach is attractive for low power applications because of low cost, high efficiency, and simple circuit design. However, to vouch for the product quality, two dc-link capacitors in the valley fill circuit should be selected to withstand the peak rectified ac input voltage. The common mode (CM) and differential mode (DM) choke should be used to suppress the electromagnetic interference (EMI) noise, thereby resulting in large size volume product. This paper presents the practical design and implementation of a valley fill flyback converter with reduced dc link capacitors and EMI magnetic volumes. By using the proposed over voltage protection circuit, dc-link capacitors in the valley fill circuit can be selected to withstand half the peak rectified ac input voltage, and the proposed CM/DM choke can be successfully adopted. The proposed circuit effectiveness is shown by simulation and experimentally verified by a 78W prototype.

• 대한기계학회논문집B
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• 제25권9호
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• pp.1201-1208
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• 2001

Variable temperature anemometer(VTA) has greater sensitivity than a conventional constant temperature anemometer(CTA). In order to design a reliable VTA system, however, an elaborate photoconductive cell stabilizing circuit which plays a key role in setting wire-overheat ratio should be firstly developed. In this study, a stabilizing circuit which adopts proportional-integral analog controller was proposed and thoroughly tested for its accuracy and reproducibility. In contrast to the available circuit suggested by Takagi, the present circuit has characteristic that the resistance of a photoconductive cell increases with the increase of input voltage, which makes the current circuit very suitable for the design of VTA. Finally, VTA adopting stabilizing circuit was made and the enhanced sensitivity of the VTA was validated experimentally by comparing the calibration curves of VTA and CTA.

• 동력기계공학회지
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• 제1권1호
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• pp.144-153
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• 1997

The magnetic levitation system is utilized in the magnetic bearing of high-speed rotor because of little friction, no lubrication, no noise and so on. The magnetic levitation system need the feedback controller for the stabilization of system, and gap sensors are generally used to measure the gap. The use of gap sensors brings out the increase of the number of troublesome, and the decrease of the control performance because of the dislocation between the measurement point and the control point. This paper presents the design of the gap estimation circuit for the sensorless method proposed by authors in the magnetic levitation system. We made the gap estimation circuit which was composed of both the superposition circuit and the measuring circuit. And we investigated the validity of the usefulness of the proposed sensorless method in the magnetic levitation system through results of actual experiment.

• 한국조명전기설비학회지:조명전기설비
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• 제11권6호
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• pp.90-95
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• 1997

고주파 유도가열을 위한 인버터의 공진회로 설계에서 인덕턴스 L의 작용과, 출력전달 요소로 사용된 변압기의 결합계수, 그리고 코일을 사용한 가열부하의 결합계수가 공진회로의 출력, 회로의 Q와 공진주파수에 큰 영향을 주고 있음을 등가회로를 도출하여 그 특성을 해석하였다. 또한 변압기를 테브난 등가회로로 구성할 경우, 변압기의 이차측 임피던스를 일차측 임피던스고 환산하면, 권선비 n$^2$에 비례 할 뿐만 아니라 결합계수 $K^2$에도 비례함을 도출하여 결합계수형 테브난 등가회로에 의한 정확성이 큰 인버터 공진회로 설계의 기초방식을 나타냈다.

• 한국생산제조학회지
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• 제18권4호
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• pp.417-422
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• 2009

The injection mold cooling circuit optimization was studied with a response surface method in the previous research. It took so much time to find an optimum solution for a large product due to an extensive amount of calculation time for the CAE analysis. In order to use the optimization technique in the actual design process, the calculation time should be much reduced. In this study, we tried to reduce the number of design variables with the concept of the close relationship between the depth and the distance of cooling channel. The optimum ratio of the distance to the depth of cooling channels for a 2-dimensional problem was 2.0 so that the optimum ratio was again sought out for 4 large automotive parts. Therefore, the number of design variables for the cooling circuit optimization can be reduced in half, resulting in much faster running time for the optimization as a design tool.