• ETRI Journal
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• v.45 no.3
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• pp.534-542
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• 2023

The large amount of secondary effects in complementary metal-oxide-semiconductor technology limits its application in the ultra-nanoscale region. Circuit designers explore a new technology for the ultra-nanoscale region, which is the quantum-dot cellular automata (QCA). Low-energy dissipation, high speed, and area efficiency are the key features of the QCA technology. This research proposes a novel, low-complexity, QCA-based one-bit digital comparator circuit for the ultra-nanoscale region. The performance of the proposed comparator circuit is presented in detail in this paper and compared with that of existing designs. The proposed QCA structure for the comparator circuit only consists of 19 QCA cells with two clock phases. QCA Designer-E and QCA Pro tools are applied to estimate the total energy dissipation. The proposed comparator saves 24.00% QCA cells, 25.00% cell area, 37.50% layout cost, and 78.11% energy dissipation compared with the best reported similar design.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.2
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• pp.325-328
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• 2022

A convolutional neural network(CNN) is widely used in the computer vision tasks, but its computing power requirement needs a design of a special circuit. Most of the computations in a CNN can be implemented efficiently in a digital circuit, but the SoftMax layer has operations unsuitable for circuit implementation, which are exponential and logarithmic functions. This paper proposes a new method to integrate the exponential and logarithmic tables of the conventional circuits into a single table. The proposed structure accesses a look-up table (LUT) only with a few maximum values, and the LUT has the result value directly. Our proposed method significantly reduces the space complexity of the SoftMax layer circuit implementation. But our resulting circuit is comparable to the original baseline with small degradation in precision.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.371-374
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• 2000

This paper proposes a 16-bit ${\times}$ 16-bit multiplier for 2 twos-complement binary numbers with tree-like structure and implements it on a FPGA. The space and time complexity analysis shows that the 16-bit Tree-like multiplier represents lower circuit complexity and computes more quickly than both Booth array multiplier md Modified array multiplier.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.262-265
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• 2000

This paper describes design of a (32, 28) Reed Solomon decoder for optical compact disk provides double error detecting and correcting capability. The most complex circuit in the RS decoder is part for solving the error location numbers from error location polynomial, and the circuit has great influence on overall decoder complexity. We use RAM based architecture with Euclid algorithm, Chien search algorithm and Forney algorithm. We have developed VHDL model and Performed logic synthesis using the SYNOPSYS CAD tool. Then, the RS decoder has been implemented with FPGA. The total umber of gate is about 11,000 gates and it operates at 20MHz.

• Proceedings of the KIEE Conference
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• 1998.07f
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• pp.2112-2114
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• 1998

A gate driver suitable for forced switch-mode power converters such as UPS and motor drive system is presented. The proposed gate driver uses regenerated snubber power and requires no separate power supply. This does not impose any additional complexity on the main switch. Experimental results show that the proposed circuit is valid.

• Journal of information and communication convergence engineering
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• v.18 no.3
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• pp.201-206
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• 2020

This paper presents a new method for controlling the current of lighting LEDs without current sensors. This method can be used as backup against LED current sensor faults. LED lighting requires a circuit with a constant current in order to maintain the same brightness when the ambient temperature changes. Therefore, we propose a new current estimation method to provide backup in case of current sensor faults based on the calculation of the inductor current. In the fabricated circuit, the average current changes from 144.03 mA to 155.97 mA when the ambient temperature changes from 0℃ to 60℃. The application of this study can enable the fabrication of a driving IC for LEDs in the form of a single chip without sensing resistors. This is expected to reduce the complexity of the peripheral circuit and enable precise feedback control.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.258-260
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• 2007

Nowadays the automotive circuit design becomes more complicated a practical modern car circuit usually contains thousands of wires. So the error connection between connector and pins becomes more difficult to be located. This paper proposes a general way to locate all error wires in an automotive circuit design. Firstly, we give an exact definition of error wire to guide our job. This definition also composes the core part of our algorithm. Then we limit the area of the error wires by several steps. During these steps, we apply breadth-first search method to step over all wires under consideration of reducing time cost. In addition, we apply bidirectional stack technique to organize the data structure for algorithm optimization. This algorithm can get a result with all error wires and doubtful wires in a very efficient way. The analysis of this algorithm shows that the complexity is linear. We also discuss some possible improvement of this algorithm.

• Proceedings of the KIEE Conference
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• 2005.07b
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• pp.1474-1476
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• 2005

Because MCCB, ELB, etc. discharge both technical and economical duty, it is important that the study of circuit breaker guarantee high-performance and realize the power distribution system with reliability. Because of complexity electrical equipment, the accident with imbalance and flicker occur often according to technical improvement. However, study of accident with harmonics remains. In this paper, the essential characteristic of circuit breaker is introduced. To analysis operation of circuit breaker, theoretical model and several simulations have been performed.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.53 no.4
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• pp.221-226
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• 2004

Power system has recently used Double-circuit Line and Multi-circuit Line in the industrial development. This has an advantage of system stability and reliability, but the complexity of the system has a disadvantage that makes it difficult to protect the power line. Double-circuit Line has two operation conditions in the Single-circuit operation and Double-circuit operation, so it has mutual impedance. To make it possible for the remaining single-line to operate independently while there is a fault with first line or when maintenance is needed, a trip region for the single-circuit operation should be set in order to set the relay trip region. An optimal trip region for each operation, a different operational conditions for the relay setting should be calculated. In this paper, trip regions of each operation condition have been compared by considering mutual impedance and fault resistance that led to the calculation of fault impedance. Also, as we know that one of the advantages in the distance relay is the back-up protection, we calculated the trip region(Zone-2) in consideration of the mutual impedance.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.53 no.4
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• pp.221-221
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• 2004

Power system has recently used Double-circuit Line and Multi-circuit Line in the industrial development. This has an advantage of system stability and reliability, but the complexity of the system has a disadvantage that makes it difficult to protect the power line. Double-circuit Line has two operation conditions in the Single-circuit operation and Double-circuit operation, so it has mutual impedance. To make it possible for the remaining single-line to operate independently while there is a fault with first line or when maintenance is needed, a trip region for the single-circuit operation should be set in order to set the relay trip region. An optimal trip region for each operation, a different operational conditions for the relay setting should be calculated. In this paper, trip regions of each operation condition have been compared by considering mutual impedance and fault resistance that led to the calculation of fault impedance. Also, as we know that one of the advantages in the distance relay is the back-up protection, we calculated the trip region(Zone-2) in consideration of the mutual impedance.