• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.3
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• pp.70-77
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• 2017

Recently, Internet of Things (IoT) and deep learning techniques have affected video surveillance systems in various ways. The surveillance features that perform detection, tracking, and classification of specific objects in Closed Circuit Television (CCTV) video are becoming more intelligent. This paper presents real-time algorithm that can run in a PC environment using only a low power CPU. Traditional tracking algorithms combine background modeling using the Gaussian Mixture Model (GMM), Hungarian algorithm, and a Kalman filter; they have relatively low complexity but high detection errors. To supplement this, deep learning technology was used, which can be trained from a large amounts of data. In particular, an SRGB(Sequential RGB)-3 Layer CNN was used on tracked objects to emphasize the features of moving people. Performance evaluation comparing the proposed algorithm with existing ones using HOG and SVM showed move-in and move-out error rate reductions by 7.6 % and 9.0 %, respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.9
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• pp.67-74
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• 2016

This paper presents a novel multiple orthogonal subcarrier modulation based UHF band RFID communication system. In tag-to-reader communication, the demonstration system can deliver 1.6 Mbps through four subcarriers. To improve data rate while suppressing increase in circuit complexity, tag employs square-waves as the subcarriers and uses individual load modulators for each subcarrier. By using multiple orthogonal subcarrier based modulation, proposed communication system can be operated under existing UHF band RFID regulation. In reader, an OFDM demodulator is used. Since the tag backscatters the reader's CW carrier, carrier frequency offset compensation is not necessary in reader demodulator. Experimental results show that the demonstration system achieves a bit error rate of 10-5 at an Eb/N0 of 10.8 dB.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.15-21
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• 2008

Several shared buses are divided hierarchically and connected with a bridge in the bus topology that consists of many components such as SoCs. Because the bridge topology is capable of the simultaneous communication of components in the several buses, the bus performance has improved definitely. However, when the inter-bus data transaction happens, the latency increases seriously in the bridge block. In this paper, a variety of bridge architectures are analyzed in the point of view of merit and demerit. Superior frying bridge topology is proposed in the aspects of performance, IP reusability, timing margin, gate count and circuit complexity. In contrast with the conventional bridge that has only a role to switch the inter-bus data, the frying bridge can communicate directly between the bus and the slave, which decreases the traffic overhead of a shared bus and improves the performance of a bridge communication.

• The Transactions of the Korea Information Processing Society
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• v.6 no.6
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• pp.1635-1645
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• 1999

In this paper, an intelligent resynthesis technique for timing optimization at the architecture-level has been studied. The proposed technique can remedy the problem which may occur in combinational timing optimization techniques applied to circuits which have the hierarchical subblock structure at the architectural-level. The approach first tries to maintain the original hierarchical subblock while minimizing the longest delay of whole circuit. This paper tries to find a new approach to timing optimization for circuits which have hierarchical structure at architectural-level, and has verified its effectiveness experimentally. We claim its usefulness from the fact that most designers design the circuits hierarchically due to the increase of design complexity.

• The Journal of the Korea Contents Association
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• v.9 no.3
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• pp.9-19
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• 2009

In this paper, we propose a novel hardware architecture to facilitate the applicable SoC chip design of H.264/SVC which has a great deal of advancement in the international standardization in recent. Moreover, a new C-model simulator based on the proposed hardware system will be presented to support optimal SoC circuit development. Since the proposed SVC decoder is consist of some hardware engine for processing of major decoding tools and core processor for software processing, the system is simply implemented with the conventional embedded system. To improve the feasibility and applicability, and reduce the decoder complexity, the hardware decoder architecture is constructed with only the consideration of IPPP structure scalability without using the full B-picture. Finally, we present results of decoder hardware implementation and decoded picture to show the effectiveness of the proposed hardware architecture and C-model simulator.

• Transactions of the Korean Society of Automotive Engineers
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• v.16 no.3
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• pp.80-86
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• 2008

Recently, controlled auto ignition(CAI) in gasoline engines are drawing more attentions due to its extremely low level of NOx emissions and potentials in lowering the fuel consumption rate. The one of the key techniques for realizing CAI combustion in engines is the control of valve system. Since the valve linkage system with higher complexity, or even earn-less valve systems, such as electro-hydraulic and electro-magnetic system, are adopted in CAI engines, it is not easy to estimate the valve lift profile from earn profiles. Therefore new measurement techniques for valve lift in CAI engines have been tried and tested. In this paper, hole type valve lift sensor was developed and tested to check the applicability in CAI engines. The valve lifts could be obtained from the sensor signal, which depends on the distance from the sensor to magnet attached to valve. Various engine speeds, ranging from 2,000 to 6,000 rpm, and valve lifts, maximum up to 9.7 mm, were tested. It was found that the sensor output for valve lift had accuracy of 98% in comparison with the basic specifications of valve lift through improvements of sensor driving circuit.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.8
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• pp.809-815
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• 2003

It is very important to get very high switching speed as well as low phase noise of frequency synthesizer in the OFDM/FH communication system. In this paper we compare the phase noises and switching speeds of the conventional PLL and digital hybrid PLL(DH-PLL) frequency synthesizer, also, we investigate the effect of phase noise on the performance of OFDM/FH communication system. DH-PLL has high switching speed property at the cost of circuit complexity and more power consumption. Unlike the conventional PLL in which the phase noise and switching speed have the trade off relationship in respect of loop filter bandwidth, DH-PLL frequency synthesizer can perform fast switching speed and low phase noise simultaneously. Under the condition of same hopping speed requirement, DH-PLL can achieve faster switching speed and lower SNR penalty compared with conventional PLL in the OFDM/FH communication system.

• The Transactions of the Korea Information Processing Society
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• v.1 no.4
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• pp.479-489
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• 1994

At the present time, it is an important problem that we are to select a transmission line code for the very-high speed optical transmission system which can confidentially transfer the original information signal sequence efficiently, as it is to be the large capacity and the economization for the optical digital transmission system to transfer the information signal sequence at the very-high speed. Therefore, this paper is to select first the proper transmission line codes for the high speed(more than Mb/s) optical transmission system of the proposed two-level unipolar transmission line codes up to date, and to decide a mBIZ (m Binary with One Zero insertion) code as an optimal transmission line code for the very-high speed optical transmission system, resulting from analyzing the performance at the requirements of the transmission line code, such as the maximum consecutive identical digits, the transmission delay time, the increasing rate of clock, the mark rate, the circuit complexity, the supervision of transmission line error, and power spectrum among the selected transmission line codes.

• Journal of IKEEE
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• v.21 no.4
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• pp.331-337
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• 2017

In this paper, we present the design of a 20MHz bandwidth 3rd-order continuous-time low-pass sigma-delta modulator with low-noise and low-power consumption. The bandwidth of the system is sufficient to accommodate LTE and other wireless network standards. The 3rd-order low-pass filter with feed-forward architecture achieves the low-power consumption as well as the low complexity. The system uses 3bit flash quantizer to provide fast data conversion. The current-steering DAC achieves low-power and improved sensitivity without additional circuitries. Cross-coupled transistors are adopted to reduce the current glitches. The proposed system achieves a peak SNDR of 65.9dB with 20MHz bandwidth and power consumption of 32.65mW. The in-band IM3 is simulated to be 69dBc with 600mVp-p two tone input tones. The circuit is designed in a 0.18-um CMOS technology and is driven by 500MHz sampling rate signal.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.6A
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• pp.379-385
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• 2003

In this paper, we propose a time constant control method for sieving local minimum problem of the multiuser detector using Hopfield neural network for synchronous multi-rate code division multiple access(CDMA) system in selective fading environments and its performance is compared with that of the parallel interference cancellation(PIC). We also assume that short scrambling codes of 256 chip length are used an uplink, suggest a simple correlation estimation algorithm and circuit complexity reduction method by using cyclostationarity property of short scrambling code.It is verified that multiuser detector using Hopfield neural network more efficiently cancels multiple access interference(MAI) and obtain better bit error rate and near-far resistant than conventional detector.