• The KIPS Transactions:PartC
• /
• v.12C no.1 s.97
• /
• pp.53-62
• /
• 2005

The NG-SDH system requires signal synchronization to synchronize incoming ethernet signal with GFP frame. The foreign nation research completes a chipset development until now and it secures a relation technique, but it does not secure a relation technique from domestic. Therefore, in this paper, we presented with signal synchronization method of Ethernet signal through GFP frame. We knew that the synchronized method of Ethernet signal through GFP-F must apply ingress & egress buffer and GFP Idle. We understood that the synchronized method of Ethernet signal through GFP-T must apply GFP Idle and $65B{\_}PAD$, and require maximum 3-bit addition & deletion of idle. Also we showed signal synchronization realization through simulation and obtained MTIE/TDEV characteristics and peak to peak jitter in egress output.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.35 no.12B
• /
• pp.1175-1182
• /
• 2010

In this paper, we implemented a digital circuit which is targeted on FPGA for estimating azimuth information and distance between aircraft and ground station. All functions for signal processing of TACAN were integrated into a FPGA. The proposed hardware consists of input interface, register file, decoder, signal generator and main controller block. The designed hardware includes a function to generating pulse pair group for azimuth information, a function to responding the interrogation of aircraft for estimating distance between aircraft and ground station, and a function to provide ID information of ground station. The proposed hardware was implemented with FPGA chipset of ALTERA and occupied with 7,071 logic elements.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.12
• /
• pp.97-102
• /
• 2011

We propose a novel displacement measurement method in the LVDT (Linear Variable Differential Transformer) structure. This proposed algorithm is independent of coil pattern, which may be implemented to PCB, or transformer component, because it is based on the signal-mapping method. we have manufactured several boards which have different coil patterns and our algorithm is ported into TMS320F2812 of TI DSP chipset. The output signal has high accuracy and high stability although PCB coil pattern are coarse.

• 한국방재학회:학술대회논문집
• /
• 2008.02a
• /
• pp.361-364
• /
• 2008

The Application Model in Wireless Sensor Networks(WSNs) consist of wireless sensor network based on sensor hardwares which is combined the micro-controller, chipset for wireless communication and sensors, middleware for dealing with data processing and user application for common service. Applications in WSN have been applied for environmental monitoring, smart factory and have concentrated the services based on remote monitoring applications which is difficult to watch the situation by human. In this paper, we described the construction model for applying for the Ubiquitous disaster prevention system and deal with its conformity. The proposed system includes the selecting the wireless sensor hardware, routing technique for u-Disaster Prevention, composition of middleware and web-interface for application services.

• Journal of Positioning, Navigation, and Timing
• /
• v.11 no.4
• /
• pp.279-286
• /
• 2022

In this paper, we designed a software library that produces integrated Global Navigation Satellite System (GNSS) / Inertial Navigation System (INS) navigation information using the raw measurements provided by the GNSS chipset, gyroscope, accelerometer and magnetometer embedded in android smartphone. Loosely coupled integration method was used to derive information of GNSS /INS integrated navigation. An application built in the designed library was developed and installed on the android smartphone. And we conducted field experiments. GNSS navigation messages were collected in the Radio Technical Commission for Maritime Service (RTCM 3.0) format by the Network Transport of RTCM via Internet Protocol (NTRIP). As a result of experiments, it was confirmed that design requirements were satisfied by deriving navigation such as three-dimensional position and speed, course over ground (COG), speed over ground (SOG), heading and protection level (PL) using the designed library. In addition, the results of this experiment are expected to be applicable to maritime navigation applications using smart device.

• Journal of Aerospace System Engineering
• /
• v.16 no.6
• /
• pp.18-23
• /
• 2022

This paper examines the electromagnetic shielding structure of ultra-high frequency (UHF) RF modules used in aircraft. Advances in electrical and electronic technologies have increased the need for electronic equipment in aircraft. High-frequency wireless devices have become integrated circuits in the form of UHF integrated circuits to support a wide range of frequencies and miniaturisation. To ensure the functionality and performance of these integrated devices in aviation, shielding is necessary to prevent unexpected electromagnetic interference, which could be detrimental to aircraft safety. A shield structure was designed to protect the RF chipset from malfunctioning, and the shielding effectiveness was improved through the application of various geometric shapes.

• Ocean and Polar Research
• /
• v.45 no.2
• /
• pp.33-42
• /
• 2023

Dissolved oxygen (DO) is a crucial parameter for assessing environmental conditions in aquatic ecosystems. However, commercial in situ dataloggers for oxygen optodes can be relatively expensive and limited in their specifications. In this paper, we present a novel design for a DO datalogger system based on the control boards family with RP2040 MCU chipset. Our design includes two types of dataloggers: a simple logging system and a programmable system for sampling rates via magnetic switches underwater for divers. We provide detailed descriptions of the system, including the MicroPython source code and drawings to aid in construction. We also discuss the various applications of our DO datalogger system in monitoring dissolved oxygen concentration in coastal waters and assessing the benthic metabolism of aquatic ecosystems. Our DO datalogger system provides an affordable and flexible option for researchers to accurately monitor DO concentrations in aquatic environments, and thereby improve our understanding of these complex ecosystems.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.20 no.5
• /
• pp.493-502
• /
• 2009

In this paper, we compare the performance of initial timing acquisition in direct sequence ultra-wideband(DS-UWB) systems with different transmit pulse shaping filters through extensive computer simulations. Simulation results show that the timing acquisition performance of the DS-UWB system, whose chip rate is 1.32 Gchip/s, employing a rectangular transmit filter is similar to that employing a square root raised cosine(SRRC) filter with an interpolation factor of 4 in the realistic UWB channels(CM1 and CM3) as well as the additive white Gaussian noise(AWGN) channel. Additionally, we present both a 24-parallel digital correlator structure and a 24-parallel processing searcher operating at a 55 MHz system clock, and then briefly discuss the initial timing acquisition procedure. Because we can adopt an 1.32 Gsample/s digital-to-analog(D/A) converter and an 1.32 Gsample/s analog-to-digital(AID) converter in the DS-UWB system by employing the rectangular transmit filter, we have a realistic solution for the DS-UWB chipset development.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.5
• /
• pp.107-114
• /
• 2004

In this paper, we present the architecture design of CDMA/TDMA modem chipset for wireless telemetry system. The wireless telemetry system a measuring data collecting system from many RTs(Remote Terminal) installed at the specific area using wireless communication technology. It consists of CU single CU (Central Unit) for collecting data and a large amount of RTs for transmitting the measuring data. We propose the hardware architecture of the modem for RT and CU. We also design those modem using Verilog HDL and synthesis them using Synopsys$^{TM}$ CAD tool. The modem of RT is implemented with 27K gates and that of CU is implemented around 220k gates using 0.6${\mu}{\textrm}{m}$ CMOS standard cell. The proposed system is implemented and tested using Altera$^{TM}$ FPGA.PGA.

• Proceedings of the Korea Society for Simulation Conference
• /
• 2001.10a
• /
• pp.440-443
• /
• 2001

As inter-network traffics grows rapidly, the router systems as a network component becomes to be capable of not only wire-speed packet processing but also plentiful programmability for quality services. A network processor technology is widely used to achieve such capabilities in the high-end router. Although providing two such capabilities, the network processor can't support a deep packet processing at nominal wire-speed. Considering QoS may result in performance degradation of processing packet. In order to achieve foster processing, one chipset of network processor is occasionally not enough. Using more than one urges to consider a problem that is, for instance, an out-of-order delivery of packets. This problem can be serious in some applications such as voice over IP and video services, which assume that packets arrive in order. It is required to develop an effective packet processing mechanism leer using more than one network processors in parallel in one linecard unit of the router system. Simulation analysis is also needed for verifying the mechanism. We propose the packet processing mechanism consisting of more than two NPs in parallel. In this mechanism, we use a load-balancing algorithm that distributes the packet traffic load evenly and keeps the sequence, and then verify the algorithm with simulation analysis. As a simulation tool, we use DEVSim++, which is a DEVS formalism-based hierarchical discrete-event simulation environment developed by KAIST. In this paper, we are going to show not only applicability of the DEVS formalism to hardware modeling and simulation but also predictability of performance of the load balancer when implemented with FPGA.