• 제목/요약/키워드: Chip control

검색결과 1,348건 처리시간 0.032초

LonWork fieldbus 기반을 가진 HVAC 공기조화기용 고성능 지능형제어모듈 개발 (A Novel Development of Distributed Intelligent Control Module Based on the LonWorks Fieldbus for Air Handling Units in the Healing, Ventilating and Air Conditioning)

  • 홍원표
    • 조명전기설비학회논문지
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    • 제18권1호
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    • pp.115-121
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    • 2004
  • 본 연구에서는 프랜트 및 빌딩자동제어 분야에서 적용이 확대 되고 있는 LonWorks 필드버스를 이용하여 기존의 공기조화시스템를 제어하고 있는 DDC제어기를 대체할 수 있도록 필드버스에서 사용이 가능한 고성능 저가의 지능형 제어모듈을 개발하였다. 이는 필드버스 기반의 AHU 전용 지능형제어기를 새로운 설계기술로 개발하고 상품화를 실현하였다. 특히 S/W부분에서도 8 bit Neuron chip에 매우 콤팩트하게 내재된 고성능 응용프로그램도 개발하였다. 공조기의 실험시스템을 구축하여 개발된 전용 제어기를 실험한 결과 밸브, 댐퍼제어 및 감시기능이 기존 DDC 제어기보다 우수함을 확인하였다.

온도센서를 사용하지 않는 MEMS 마이크로히터 온도제어시스템 (A Sensorless and Versatile Temperature-Control System for MEMS Microheaters)

  • Bae, Byung-Hoon;Yeon, Jung-Hoon;Flachsbart Bruce R.;Shannon Mark A.
    • 대한전기학회논문지:전기물성ㆍ응용부문C
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    • 제55권11호
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    • pp.544-547
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    • 2006
  • In this paper, we present a temperature-controlled system for MEMS electrical resistance heaters without a temperature sensor. To rapidly control the heater temperature, the microheater system developed consists of a power supply, power amplifier, digital ${\underline{P}}roportional-{\underline{I}}ntegral-{\underline{D}}ifferential$ (PID) controller, and a quarter bridge circuit with the microheater and three resistors are nominally balanced. The microheaters are calibrated inside a convection oven to obtain the temperature coefficient with a linear or quadratic fit. A voltage amplifier applies the supply voltage proportional to the control signal from the PID controller. Small changes in heater resistance generate a finite voltage across the quarter bridge circuit, which is fed back to the PID controller to compare with the set-point and to generate the control signal. Two MEMS microheaters are used for evaluating the developed control system - a NiCr serpentine microheater for a preconcentrator and a Nickel microheater for ${\underline{P}}olymerase\;{\underline{C}}hain\;{\underline{R}}eaction$ (PCR) chip.

엔드밀 가공시 비례적분제어를 이용한 커터 런아웃 보상에 관한 연구 (A Study on the Cutter Runout Compensation by PI Control in End Mill Process)

  • 이기용;황준;정의식
    • 한국정밀공학회지
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    • 제15권5호
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    • pp.65-71
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    • 1998
  • This paper presents in-process compensation methodology to eliminate cutter runout and improve machined surface quality. The cutter runout compensation system consists of the micro-positioning mechanism with the PZT (piezo-electric translator) which is embeded in the sliding table to manipulate the radial depth of cut in real time. For the implementation of cutter runout compensation methodology. cutting force adaptive control was proposed in the angle domain based upon PI (proportional-integral) control strategy to eliminate chip-load change in end milling process. Micro-positioning control due to adaptive acuation force response improves the machined surface quality by compensation or elimination of cutter runout induced cutting force variation. This results will provide lots of information to build-up the precision machining technology.

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RAPTOR의 명령어 페치 유닛 설계 (Design of an Instruction Fetch Unit for RAPTOR, a On-Chip Multiprocessor)

  • 이성권;오형철이상원한우종
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 1998년도 추계종합학술대회 논문집
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    • pp.767-770
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    • 1998
  • This paper introduces an instruction fetch unit which is designed for RAPTOR, an on-chip multiprocessor. In order to reduce control hazards, the proposed fetch unit supports a hybrid branch prediction scheme which consists of a static scheme and the 2bC branch prediction scheme. The fetch unit also utilizes the branch folding technique with two instruction buffers to avoid the branch penalty caused by imspredictions. Instructions are predecoded in the fetch unit to achieve extra performance gain.

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DSP 기반 통신 소프트웨어의 설계 및 테스트베드 (Design of Communication Software Based on DSP and Implementation of Testbed)

  • 황택규
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 1999년도 하계종합학술대회 논문집
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    • pp.1137-1140
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    • 1999
  • In this thesis, we research about Communication System Construction and Test-Bed Realization Method and Software’s Design with written program into Embedded Micro Controller’s restricted memory region using a DSP Chip to deal with mainly high speed communication. Tools used for modern communication network control use TI or AMD general chip class, but nevertheless responsibility for the point at issue, Analog Device is architecture design model moderated for small communication system. In this thesis, we present extended model, and realize basic case.

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MPEG2용 IEEE1394 LINK CHIP SET 개발 기술

  • 이희
    • 정보화사회
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    • 통권129호
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    • pp.42-49
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    • 1999
  • 디지털 비디오의 혁명이 가시화 되면서 가정의 각 Consumer기기들 간의 고속 Digital Interface가 요구되어져 왔다. 이러한 요구의 예는 MPEG-2 Transport Stream을 이용한 Set-Top Bx, Digital Television, DVCR 또는 Camcorder간의 Interface와 Interactive Games, Computers 및 주변기기간의 Control/Data Interface를 포함하고 있다. 엄밀히 말해 Data의 일반적인 전송을 지원하는 Interface가 요구되어지며, IEEE1394 Standard는 이에 대한 최적의 Solution을 제공해 준다. 본 기술은 IEEE1394를 기반으로 MPEG-2 Transport Stream을 주고받을 수 있는 방법을 제공하기 위한 Hardware를 개발하는 기술인 MPEG2용 IEEE1394 Link Chip Set 개발 기술에 대하여 설명한다.

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유전자 알고리즘을 이용한 멀티헤드 겐트리타입 칩마운터의 장착순서 최적화 (A Mount Sequence Optimization for Multihead-Gantry Chip Mounters Using Genetic Algorithm)

  • 이재영;박태형
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2003년도 하계학술대회 논문집 D
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    • pp.2450-2452
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    • 2003
  • We present a method to increase the productivity of multihead-gantry chip mounters for PCB assembly lines. To minimize the assembly time, we generate the mount sequence using the genetic algorithm. The chromosome, fitness function, and operators are newly defined to apply the algorithm. Simulation results are presented to verified the usefulness of the method.

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수축율 조절에 의한 적층 칩 LC Filter의 동시 소성에 관한 연구 (A Study on Co-Firing of Multilayer Chip LC Filter by Control of Shrinkage)

  • 김경용;이종규;김왕섭;최환
    • 한국세라믹학회지
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    • 제28권9호
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    • pp.675-682
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    • 1991
  • Among many problems that need to be solved in the process of preparing multilayer chip LC filters, we studied the control of shrinkage in order to prevent the crack, warpage, and/or delamination which occurs at the interface between the inductance (L part) and the capacitance (C part). Shrinkage was controlled by compositions, powder size, calcining temperature and amount of organic binder. Capacitance sheet was prepared by mixing 65 wt% binder with the composition of 96 wt% TiO2 having an average particle size of 0.5 $\mu\textrm{m}$, 3 wt% CuO. After small amount of MnO2 and SiO2 added, it was calcined at 750$^{\circ}C$ for 2 hr. Inductance sheet was prepared by mixing 60 wt% binder with the composition of 49.5% mol% Fe2O3, 20.5 mol% ZnO, 20 mol% NiO and 10 mol% CuO which was calcined at 775$^{\circ}C$ for 2 hr. These sheets was laminated at 250 kg/$\textrm{cm}^2$, and cofired at 900$^{\circ}C$ for 2 hr to give rise to a multilayer chip LC filter without any warpage.

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