• Proceedings of the Korean Society of Precision Engineering Conference
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• 2000.11a
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• pp.801-805
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• 2000

This paper presents a new method of tool path optimization. A NC verification model based Z-map was utilized to obtain chip load in feed per tooth. This developed software can regenerate a NC program from cutting condition and the NC program that was generated in CAM. The regenerated NC program has not only all same data of the ex-NC program but also the new feed rates in every block. The new NC data can reduce the cutting time and manufacture precision dies with the same chip load in feed per tooth. This method can also prevent tool chipping and make constant tool wear. This paper considered the effects of acceleration and deceleration in feed rate change.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1995.10a
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• pp.151-156
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• 1995

This paper presents a methodology for real-time detecting and identifying the runout geometry of an end mill. Cutter runout is a common but undesirable phenomenon in multi-tooth machining such as end-milling process because it introduces variable chip loading to insert which results in a accelerated tool wear,amplification of force variation and hence enlargement vibration amplitude. Form understanding of chip load change kinematics, the analytical sutting force model was formulated as the angular domain convolution of three dynamic cutting force component functions. By virtue of the convolution integration property, the frequency domain expression of the total cutting forces can be given as the algebraic multiplication of the Fourier transforms of the local cutting forces and the chip width density of the cutter. Experimental study are presented to validata the analytical model. This study provides the in-process monitoring and compensation of dynamic cutter runout to improve machining tolerance tolerance and surface quality for industriql application.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.10 no.1
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• pp.42-48
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• 2011

In this paper, a passive load-pull using a GaN HEMT (Gallium Nitride High Electron Mobility Transistor) bare-chip in X-band is presented. To obtain operation conditions that characteristic change by self-heating was minimized, pulsed drain bias voltage and pulsed-RF signal is employed. An accuracy impedance matching circuits considered parasitic components such as wire-bonding effect at the boundary of the drain is accomplished through the use of a electro-magnetic simulation and a circuit simulation. The microstrip line length-tunable matching circuit is employed to adjust the impedance. The measured maximum output power and drain efficiency of the pulsed load-pull are 42.46 dBm and 58.7%, respectively, across the 8.5-9.2 GHz band.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.11a
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• pp.21-26
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• 2002

Solder flip chip bumping and subsequent coining processes on PCB were investigated to solve the warpage problem of organic substrates for high pin count flip chip assembly by providing good co-planarity. Coining of solder bumps on PCB has been successfully demonstrated using a modified tension/compression tester with height, coining rate and coining temperature variables. It was observed that applied loads as a function of coined height showed three stages as coining deformation : (1) elastic deformation at early stage, (2) linear increase of applied load, and (3) rapid increase of applied load. In order to reduce applied loads for coining solder bumps on PCB, effects of coining process parameters were investigated. Coining loads for solder bump deformation strongly depended on coining rates and coining temperatures. As coining rates decreased and process temperature increased, coining loads decreased. Among the effect of two factors on coining loads, it was found that process temperature had more significant effect to reduce applied coining loads during the coining process. Lower coining loads were needed to prevent substrate damages such as micro-via failure and build-up dielectric layer thickness change during applying loads. For flip chip assembly, 97Pb/Sn flip chip bumped devices were successfully assembled on organic substrates with 37Pb/Sn coined flip chip bumps.

• Proceedings of the KIEE Conference
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• 1998.11a
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• pp.179-181
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• 1998

In this paper, one chip PWM pattern generator which eliminates time delay of computations and improves utilization factor of voltage is proposed. Both amplitude of sinusoidal signal and triangular signal are directly controlled. Thus, time delay of computations can be eliminated, and it is possible to track accurately instantaneous current for a sudden change of load with microprocessor 80C196KC. In addition, setting dead-time is also possible for wide range. From experimental work with inverter system for driving induction motor, the validity of proposed one chip PWM pattern generator is verified.

• Journal of Power Electronics
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• v.9 no.3
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• pp.507-515
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• 2009

This paper proposes an autonomous decentralized control for a parallel connected uninterruptible power supply (UPS) system based on a fast power detection method using a FPGA based hardware controller for a single phase system. Each UPS unit detects only its output voltage and current without communications signal exchange and a quasi dq transformation method is applied to detect the phase and amplitude of the output voltage and the output current for the single phase system. Fast power detection can be achieved based on a quasi dq transformation, which results in a realization of very fast transient response under rapid load change. In the proposed method, the entire control system is implemented in one FPGA chip. Complicated calculations are assigned to hardware calculation logic, and the parallel processing circuit makes it possible to realize minimized calculation time. Also, an Nios II CPU core is implemented in the same FPGA chip, and the software can be applied for non-time critical calculations. Applying this control system, an autonomous decentralized UPS system with very fast transient response is realized. Feasibility and stable operation are confirmed by means of an experimental setup with three UPSs connected in parallel. Also, rapid load change is applied and excellent performance of the system is confirmed in terms of transient response and stability.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.7 no.2
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• pp.91-99
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• 1998

This paper presents a methodology for identifying the cutter runout geometry in end milling process. Cutter runout is common but undesirable phenomenon in multi-tooth machining because it introduces variable chip loading to insert which results in a accelerated tool wear. amplification of force variation and hence enlargement vibration amplitude From understanding of chip load change kinematics, the analytical cutting force convolution model was formulated as the angular domain convolution model was formulated as the angular domain convolution of three dynamic cutting force component functions. By virtue of the convolution integration property, the frequency domain expression of the local cutting forces and the chip width density of the cutter. Experimental study is presented to validate the analytical model. This study provides the in-process monitoring and compensation of dynamic cutter runout to improve machining tolerance and surface quality for industrial application.

• Journal of the Korean Society for Precision Engineering
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• v.15 no.5
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• pp.65-71
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• 1998

This paper presents in-process compensation methodology to eliminate cutter runout and improve machined surface quality. The cutter runout compensation system consists of the micro-positioning mechanism with the PZT (piezo-electric translator) which is embeded in the sliding table to manipulate the radial depth of cut in real time. For the implementation of cutter runout compensation methodology. cutting force adaptive control was proposed in the angle domain based upon PI (proportional-integral) control strategy to eliminate chip-load change in end milling process. Micro-positioning control due to adaptive acuation force response improves the machined surface quality by compensation or elimination of cutter runout induced cutting force variation. This results will provide lots of information to build-up the precision machining technology.

• Journal of Institute of Control, Robotics and Systems
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• v.3 no.4
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• pp.363-372
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• 1997

In this paper, the design and the implementation of the adaptive learning rate neural network controller for an articulate robot, which is being developed (or) has been developed in our Automatic Control Laboratory, are mainly discussed. The controller reduces software computational load via distributed processing method using multiple CPU's, and simplifies hardware structures by the time-division control with TMS32OC31 DSP chip. Proposed neural network controller with adaptive learning rate structure using expert's heuristics can improve learning speed. The proposed controller verifies its superiority by comparing response characteristics of conventional controller with those of the proposed controller that are obtained from the experiments for the 5 axis vertical articulated robot. We, also, present the generalization property of proposed controller for unlearned trajectory and the change of load through experimental data.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.31-40
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• 2009

This paper presents a design of a high performance DC-DC boost converter as a power module for SOC designs. It applied to this chip that reduced inductor and capacitor for integrating on a chip, and it operates with a switching frequency of 100MHz. It has reliability and stability in high switching frequency. The controller of DC-DC boost converter is designed by voltage-mode control method and compensated properly. The designed DC-DC converter is fabricated with the 0.18${\mu}m$ standard CMOS technology with a thick-gate oxide option. The overall die size is 8.14$mm^2$, and controller size is 1.15$mm^2$. The converter has the maximum efficiency over 76% for the output voltage of 4V and load current larger 300mA. The load regulation is 0.012% (0.5mV) for the load current change of 100mA.