• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.37-43
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• 2008

In this paper, the dependence of electrical characteristics of Silicon-$Al_2O_3$-Nitride-Oxide-Silicon (SANOS) memory cell transistors and program/erase (P/E) speed, reliability of memory device on interface trap between Si substrate and tunneling oxide and bulk trap in nitride layer were investigated using charge pumping method which has advantage of simple and versatile technique. We analyzed different SANOS memory devices that were fabricated by the identical processing in a single lot except the deposition method of the charge trapping layer, nitride. In the case of P/E speed, it was shown that P/E speed is slower in the SANOS cell transistors with larger capture cross section and interface trap density by charge blocking effect, which is confirmed by simulation results. However, the data retention characteristics show much less dependence on interface trap. The data retention was deteriorated as increasing P/E cycling number but not coincides with interface trap increasing tendency. This result once again confirmed that interface trap independence on data retention. And the result on different program method shows that HCI program method more degraded by locally trapping. So, we know as a result of experiment that analysis the SANOS Flash memory characteristic using charge pumping method reflect the device performance related to interface and bulk trap.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.94-95
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• 2007

In this paper, the dependence of electrical characteristics of Silicon-$Al_2O_3$-Nitride-Oxide-Silicon (SANOS) memory cell transistors and program speed, reliability of memory device on interface trap between Si substrate and tunneling oxide was investigated. The devices were fabricated by the identical processing in a single lot except the deposition method of the charge trapping layer, nitride. In the case of P/E speed, it was shown that P/E speed is slower in the SONOS cell transistors with larger interface trap density by charge blocking effect, which is confirmed by simulation results. However, the data retention characteristics show much less dependence on interface trap. Therefore, to improve SANOS memory characteristic, it is very important to optimize the interface trap and charge trapping layer.

• Electrical & Electronic Materials
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• v.7 no.3
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• pp.231-235
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• 1994

The multi-dielectric layer $SiO_2$/$Si_3{N_4}$/$SiO_2$ (ONO) is used to improve charge retention and to scale down the memory device. The nitride layer of MNOS device is oxidize to form ONO system. During the oxidation of the nitride layer, the change of thickness of nitride layer and generation of interface state between nitride layer and top oxide layer occur. In this paper, effects of oxidation of the nitride layer is studied. The decreases of the nitride layer due to oxidation and trapping characteristics of interface state of multi layer dielectric film are investigated through the C-V measurement and F-N tunneling injection experiment using SONOS capacitor structure. Based on the experimental results, carrier trapping model for maximum flatband voltage shift of multi layer dielectric film is proposed and compared with experimental data. As a results of curve fitting, interface trap density between the top oxide and layer is determined as being $5{\times}10^11$~$2{\times}10^12$[$eV^1$$cm^2$].