• Title/Summary/Keyword: Cell array

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Cell Searching and DoA Estimation Methods for a Mobile Relay Station with a Uniform Circular Array (원형 등간격 어레이를 갖는 이동 릴레이의 셀 탐색과 입사각 추정기법)

  • Ko, Yo-Han;Kim, Yeong-Jun;Yoo, Hyun-Il;Cho, Yong-Soo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.34 no.9A
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    • pp.664-672
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    • 2009
  • In this paper, joint methods of cell searching and Direction-of-Arrival (DoA) estimation for a mobile relay station with a uniform circular array are proposed. The proposed joint estimation method for the mobile relay station is robust even when there exist symbol timing offsets between the signals received from adjacent base stations. Also, the proposed joint estimation method can reduce computational complexity and processing time, compared with the case where cell searching and DoA estimation are performed separately. Performances of the proposed method are evaluated by computer simulation under Mobile WiMAX environment.

Design and Implementation of the Systolic Array for Dynamic Programming

  • Lee, Jae-Jin;Tien, David;Song, Gi-Yong
    • Journal of the Institute of Convergence Signal Processing
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    • v.4 no.3
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    • pp.61-67
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    • 2003
  • We propose a systolic array for dynamic programming which is a technique for solving combinatorial optimization problems. We derive a systolic array for single source shortest path Problem, SA SSSP, and then show that the systolic array serves as dynamic Programming systolic array which is applicable to any dynamic programming problem by developing a systolic array for 0 1 knapsack problem, SA 01KS, with SA SSSP for a basis. In this paper, each of SA SSSP and SA 01KS is modeled and simulated in RT level using VHDL, then synthesized to a schematic and finally implemented to a layout using the cell library based on 0.35${\mu}{\textrm}{m}$ 1 poly 4 metal CMOS technology.

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Improvement of Control Performance of Array-Sensor System Using Soft Computing (Soft Computing을 이용한 배열 센서 시스템의 제어 성능 개선)

  • Na, Seung-You;Ahn, Myung-Kook
    • Journal of Sensor Science and Technology
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    • v.12 no.2
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    • pp.79-87
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    • 2003
  • In this paper, we propose a method to obtain a linear characteristic using soft computing for systems which have array sensors of nonlinear characteristics. Also a procedure utilizing the pattern information of array sensors without additional sensors is proposed to reduce disturbance effects. For a typical example, even a single CdS cell for CdS array has nonlinear characteristics. Overall linear characteristic for CdS array is obtained using fuzzy logic for each cell and overlapped portion. In addition, further improvement for linearization is obtained applying genetic algorithms for the parameters of membership functions. Also the effect of disturbing external light changes to the CdS array can be reduced without using any additional sensors for calibration. The proposed method based on fuzzy logic shows improvements for position measurements and disturbance reduction to external light changes due to the fuzziness of the shadow boundary as well as the inherent nonlinearity of the CdS array. This improvement is shown by applying the proposed method to the ball position measurements of a magnetic levitation system.

MAXIMUM POWER POINT TRACKING CONTROL OF PHOTOVOLTAIC ARRAY USING FUZZY NEURAL NETWORK

  • Tomonobu Senjyu;Yasuyuki Arashiro;Katsumi Uezato;Hee, Han-Kyung
    • Proceedings of the KIPE Conference
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    • 1998.10a
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    • pp.987-992
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    • 1998
  • Solar cell has an optimum operating point to extract maximum power. To control operating point of the solar cell, a fuzzy controller has already been proposed by our research group. However, several parameters are determined by trial and error. To overcome this problem, this paper adopts Fuzzy Neural Network (FNN) for maximum power point tracking control for photovoltaic array. The FNN can be trained to perfect fuzzy rules and to find an optimum membership functions on-line.

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IDENTIFICATION OF GENES INVOLVED IN OSTEOCLAST DIFFERENTIATION BY CDNA ARRAY ANALYSES (dDNA array를 이용한 파골세포 분화 관련 유전자의 탐색)

  • Cho, Young-Jun;Lee, Zang-Hee;Lee, Chang-Seop;Lee, Sang-Ho
    • Journal of the korean academy of Pediatric Dentistry
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    • v.29 no.2
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    • pp.278-284
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    • 2002
  • To examine the global gene expression of osteoclastogenesis-related genes in RAW 264.7 and its differentiated OCLs through the use of Atlas Mouse cDNA Array 2.1 membranes printed with 1176 well-characterized mouse genes involved in biology. Both samples were screened in parallel using cDNA expression arrays. The array results were additionally validated using RT-PCR. The results of cDNA arrays showed that 6 genes were up-regulated >2.5-fold (PKC beta II. POMC, PTEN, etc) and 16 genes were down-regulated >2.5-fold (Osteopontin, Cyclin D1, Cathepsin C, PTMA, etc) in both samples at the mRNA level. RT-PCR analysis of PKC beta II of these differentially expressed genes gave result consistent with cDNA array findings. The result of osteoclastogenesis showed that the PKC beta II gene was overexpressed in OCLs compared with RAW264.7 cell line. Osteoclastogenesis-related genes are differentially expressed in RAW264.7 cell line and its differentiated OCLs. its gene overexpression correlates with osteoclast differentiation in RAW264.7 cell line.

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A study of Recess Channel Array Transistor with asymmetry channel for high performance and low voltage Mobile 90nm DRAMs (고성능 저전압 모바일향 90nm DRAM을 위한 비대칭 채널구조를 갖는 Recess Channel Array Transistor의 제작 및 특성)

  • Kim, S.B.;Lee, J.W.;Park, Y.K.;Shin, S.H.;Lee, E.C.;Lee, D.J.;Bae, D.I.;Lee, S.H.;Roh, B.H.;Chung, T.Y.;Kim, G.H.
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2004.11a
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    • pp.163-166
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    • 2004
  • 모바일향 90nm DRAM을 개발하기 위하여 비대칭 채널 구조를 갖는 Recess Channel Array Transistor (RCAT)로 cell transistor를 구현하였다. DRAM cell transistor에서 junction leakage current 증가는 DRAM retention time 열화에 심각한 영향을 미치는 요인으로 알려져 있으며, DRAM의 minimum feature size가 점점 감소함에 따라 short channel effect의 영향으로 junction leakage current는 더욱 더 증가하게 된다. 본 실험에서는 short channel effect의 영향에 의한 junction leakage current를 감소시키기 위하여 Recess Channel Array Transistor를 도입하였고, cell transistor의 채널 영역을 비대칭으로 형성하여 data retention time을 증가시켰다. 비대칭 채널 구조을 이용하여 Recess Channel Array Transistor를 구현한 결과, sub-threshold 특성과 문턱전압, Body effect, 그리고, GIDL 특성에는 큰 유의차가 보이지 않았고, I-V특성인 드레인 포화전류(IDS)는 대칭 채널 구조인 transistor 대비 24.8% 정도 증가하였다. 그리고, data retention time은 2배 정도 증가하였다. 본 실험에서 얻은 결과는 향후 저전압 DRAM 개발과 응용에 상당한 기여를 할 것으로 기대된다.

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Noble Development of Array Type Gripper for Robot Arm

  • Lee, Jaeman;Lee, Wangheon
    • Journal of the Korean Society of Industry Convergence
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    • v.25 no.2_1
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    • pp.185-193
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    • 2022
  • For grippers of industrial robots, parallel grippers and multi-function finger grippers are used. The former has the advantage of low cost but has the disadvantage of low precision, and the latter has the advantage of excellent precision but has the disadvantage of being expensive. In this paper, we developed a grip that can detects the various shapes of the object to be gripped on the gripper surface by using mesured pressure information frome Veloset Sheet sensor so that the gripper can be gripped without deforming the surface of the gripper. Also we did not only developed the array type gripper and 4 array type grippers (ATG), but also confirmed the usefulness of array type gripper developed in this study according to the 4 predefined evaluation criteria

Development of Metal Substrate with Multi-Stage Nano-Hole Array for Low Temperature Solid Oxide Fuel Cell (저온 고체산화물연료전지 구현을 위한 다층 나노기공성 금속기판의 제조)

  • Kang, Sangkyun;Park, Yong-Il
    • Journal of the Korean Ceramic Society
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    • v.42 no.12 s.283
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    • pp.865-871
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    • 2005
  • Submicron thick solid electrolyte membrane is essential to the implementation of low temperature solid oxide fuel cell, and, therefore, development of new electrode structures is necessary for the submicron thick solid electrolyte deposition while providing functions as current collector and fuel transport channel. In this research, a nickel membrane with multi-stage nano hole array has been produced via modified two step replication process. The obtained membrane has practical size of 12mm diameter and $50{\mu}m$ thickness. The multi-stage nature provides 20nm pores on one side and 200nm on the other side. The 20nm side provides catalyst layer and $30\~40\%$ planar porosity was measured. The successful deposition of submicron thick yttria stabilized zirconia membrane on the substrate shows the possibility of achieving a low temperature solid oxide fuel cell.

Preparation and Characterization of Genetically Engineered Mesenchymal Stem Cell Aggregates for Regenerative Medicine

  • Kim, Sun-Hwa;Moon, Hyung-Ho;Chung, Bong-Genn;Choi, Dong-Hoon
    • Journal of Pharmaceutical Investigation
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    • v.40 no.6
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    • pp.333-337
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    • 2010
  • Combining cell- and gene-based therapy is a promising therapeutic strategy in regenerative medicine. The aim of this study was to develop genetically modified mesenchymal stem cell (MSC) aggregates using a poly(ethylene glycol) (PEG) hydrogel micro-well array technique. Stable PEG hydrogel micro-well arrays with diameters of 200 to $500\;{\mu}m$ were fabricated and used to generate genetically engineered MSC aggregates. Rat bone marrow-derived MSCs were transfected with a green fluorescent protein (GFP) plasmid as a reporter gene, and aggregated by culturing in the PEG hydrogel micro-well arrays. The resultant cell aggregates had a mean diameter of less than $200\;{\mu}m$, and maintained the mesenchymal phenotype even after genetic modification and cell aggregation. Transplantation of MSC aggregates that are genetically modified to express therapeutic or cell-survival genes may be a potential therapeutic approach for regenerative medicine.

A Study on the Design of Format Converter for Pixel-Parallel Image Processing (픽셀-병렬 영상처리에 있어서 포맷 컨버터 설계에 관한 연구)

  • 김현기;김현호;하기종;최영규;류기환;이천희
    • Proceedings of the IEEK Conference
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    • 2001.06b
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    • pp.269-272
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    • 2001
  • In this paper we proposed the format converter design and implementation for real time image processing. This design method is based on realized the large processor-per-pixel array by integrated circuit technology in which this two types of integrated structure is can be classify associative parallel processor and parallel process with DRAM cell. Layout pitch of one-bit-wide logic is identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilized the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start

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