• 전력전자학회논문지
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• 제22권4호
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• pp.369-372
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• 2017

This paper presents a control scheme for three-level NPC inverters using small DC-link capacitors. To reduce the inverter system volume, the film capacitor with small capacitance is a promising candidate for the DC-link. When small capacitors are applied in a three level inverter, however, the AC ripple component increases in the DC-link NPV (neutral point voltage). In addition, the three-phase input grid currents are distorted when the DC-link capacitors are fed by diode rectifier. In this paper, the additional circuit is applied to compensate for small capacitor systems defect, and the offset voltage injection method is presented for the stabilization in NPV. These two proposed processes evidently ensure the quality improvement of the input grid currents and output load currents. The feasibility of the proposed method is verified by experimental results.

• KIEE International Transactions on Electrophysics and Applications
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• 제4C권3호
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• pp.96-100
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• 2004

The Nd： YAG laser is commonly used throughout many fields such as accurate material processing, IC marking, semiconductor annealing, medical operation devices, etc., due to the fact that it has good thermal and mechanical properties and is easy to maintain. In materials processing, it is essential to vary the laser power density for specific materials. The laser power density can be mainly controlled by the current pulse width and pulse repetition rate. It is important to control the laser energy in those fields using a pulsed laser. In this paper we propose the constant-frequency current resonant half-bridge converter and monitoring of capacitor charging voltage. This laser power supply is designed and fabricated to have less switching loss, compact size, isolation with primary and secondary transformers, and detection of capacitor charging voltage. Also, the output stabilization characteristics of this Nd： YAG laser system are investigated. The test results are described as a function of laser output energy and flashlamp arc discharging constant. At the energy storage capacitor charges constant voltage, the laser output power is 2.3％ error range in 600[V].

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 제4회 영호남학술대회 논문집
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• pp.109-122
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• 2002

The standard capacitor must have not only precise value of the capacitance but also the basic properties of low dielectric loss tangent. In the reforming process of capacitors, the dielectric loss tangent must be also reformed. In this paper, the development of standard capacitors of 10 and 100pF for the dielectric loss tangent standard using $Al_{2}O_{3}$ Crystal and the measurement of dielectric loss tangent are discussed. The dielectric loss tangent depends upon the surface between electrode and dielectric in capacitor. With using the Electric Field Simulator, precise design values of electrode are simulated. For the purpose of measuring capacitance effect just in the dielectric, 3-Terminal and 4-Terminal Pair configuration are applied respectively at the electrode and the connector for the measuring equipment. As stated above method, the standard capacitors of 10 and l00pF for the establishment of the dielectric loss tangent standard using the $Al_{2}O_{3}$ Crystal are made with low dielectric loss tangent less than 10-4.

• 전기전자학회논문지
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• 제23권2호
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• pp.407-412
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• 2019

LED 조명은 많은 장점으로 인하여 다양한 분야에서 사용이 점점 증가되고 있다. 특히 플라이백 컨버터는 전력밀도와 구조적 단순성 그리고 소형화가 가능하여 많은 컨버터 설계자들에게 LED 조명용 드라이버로 선택되어지고 있다. 또한 컨버터의 직류출력전압을 안정화하기 위하여 저렴한 가격의 정전용량이 큰 전해커패시터를 사용한다. 전해 커패시터를 갖는 전력변환기를 LED 조명시스템에 적용할 경우에 일반적으로 LED의 수명이 짧아지는 결과를 가져온다. 제안하는 논문은 LED 수명연장과 컨버터 출력리플을 감소시키기 위하여 소용량의 필름 커패시터 LC 필터를 컨버터에 적용하였다.

• Journal of Biosystems Engineering
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• 제43권2호
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• pp.94-102
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• 2018

Purpose: In this study, a maintenance free super-capacitor battery charging system based on the photovoltaic module, to be used in agricultural electric carriers, was developed and its charging characteristics were studied in detail. Methods: At first, the electric carrier system configuration is introduced and the electric control components are presented. The super-capacitor batteries and photovoltaic module used in the experiment are specified. Next, the developed charging system consisting of a constant current / constant voltage Buck converter as the charging device and a super-capacitor cell as a balancing device are initiated. The proposed circuit design, a developed PCB layout of each device and a proportional control to check the current and voltage during the charging process are outlined. An experiment was carried out using a developed prototype to clarify the effectiveness of the proposed system. A power analyzer was used to measure the current and voltage during charging to evaluate the efficiency of the energy storage device. Finally, the conclusions of this research are presented. Results: The experimental results show that the proposed system successfully controls the charging current and balances the battery voltage. The maximum voltage of the super-capacitor battery obtained by using the proposed battery charger is 16.2 V, and the maximum charging current is 20 A. It was found that the charging time was less than an hour through the duty ratio of 95% or more. Conclusions: The developed battery charging system was successfully implemented on the agricultural electric carriers.

• 한국전자통신학회논문지
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• 제15권3호
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• pp.487-494
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• 2020

본 논문에서는 정적소비전력을 줄이며, 전류 모드 신호처리의 장점을 최대로 올릴 수 있는 전류 메모리 회로 설계를 제안한다. 제안하는 전류 메모리 회로는 기존의 전류 메모리 회로가 갖는 Clock-Feedthrough와 Charge-Injection 등으로 인해 데이터 저장 시간이 길어지면서 전류 전달 오차가 심해지는 문제를 최소화하며, 저전력 동작이 가능한 Current Transfer 구조에 밀러 효과(Miller effect)를 극대화하는 Support MOS Capacitor를 삽입하는 설계로, 저장 시간에 따르는 개선된 전류 전달 오차를 보였다. 매그나칩/SK하이닉스 0.35㎛ 공정으로 칩 제작을 통한 실험 결과, 저장 시간에 따르는 전류 전달 오차가 5% 이하로 개선되는 것을 검증하였다.

• 한국세라믹학회지
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• 제40권11호
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• pp.1090-1095
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• 2003

본 논문에서는 고품질 적층형 수동 소자의 모델링 및 설계에 관하여 연구하였고, 설계된 수동 소자를 이용하여 안테나 스위치 모듈 내에 포함된 이중 대역 GSM/DCS 대역 분리용 적층형 다이플렉서를 설계$.$제작하여 그 특성을 고찰하였다. 적층형 수동 소자는 시스템의 소형화를 위해 인덕터는 정방형 스파이럴 구조로, 캐패시터는 입체적인 인터디지털 형태인 VIC 구조로 설계하였다. GSM 저역 통과 필터는 0.55 dB 이하의 삽입 손실과 12dB 이상의 반사 손실을 나타내며, 통과 대역 위쪽 저지 대역인 1800 MHz 부근에 감쇠극이 존재하도록 설계함으로써 DCS 통과 대역에서 26 dB 이상의 저지 특성을 나타내었다. DCS 고역 통과 필터는 0.82 dB 이하의 삽입 손실과 11 dB 이상의 반사손실을 가지며, 통과 대역 아래 쪽 저지 대역인 930 MHz 부근에 감쇠극이 존재하도록 설계함으로써 GSM 통과 대역에서 38 dB 이상의 저지 특성을 나타내었다.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2014년도 추계학술대회
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• pp.569-572
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• 2014

본 논문에서는 MEMS 용량형 센서를 위한 CMOS 스위치드-커패시터 인터페이스 회로를 설계하였다. 설계된 회로는 커패시턴스-전압 변환기(CVC), 2차 스위치드 커패시터 ${\Sigma}{\Delta}$ 변조기 및 비교기로 구성되어있다. 또한 일정한 바이어스를 공급해주는 바이어스 회로를 추가하였다. 전체적인 회로의 저주파 잡음과 오프셋을 감소시키기 위하여 Correlated-Double-Sampling(CDS) 기법과 Chopper-Stabilization(CHS) 기법을 적용하였다. 설계 결과 CVC는 20.53mV/fF의 민감도와 0.036%의 비선형성특성을 보였으며, ${\Sigma}{\Delta}$ 변조기는 입력전압 진폭이 100mV가 증가할 때, 출력의 듀티 싸이클은 약 5%씩 증가하였다. 전체회로의 선형성 에러는 0.23% 이하이며, 전류소모는 0.73mA이다. 제안된 회로는 0.35um CMOS 공정을 이용하여 설계되었으며, 입력전압은 3.3V이다. 설계된 칩의 크기는 패드를 포함하여 $1117um{\times}983um$ 이다.

• Journal of Power Electronics
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• 제17권2호
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• pp.570-578
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• 2017

This paper proposes a method to stabilize the output voltage of the secondary side of an Inductive Power Transfer (IPT) system through tuning/detuning via a serial tuned DC Voltage-controlled Variable Capacitor (DVVC). The equivalent capacitance of the DVVC changes with the conduction period of a diode in the DVVC controlled by DC voltage. The output voltage of an IPT system can be made constant when this DVVC is used as a variable resonant capacitor combined with a PI controller generating DC control voltage according to the fluctuations of the output voltage. Since a passive diode instead of an active switch is used in the DVVC, there are no active switch driving problems such as a separate voltage source or gate drivers, which makes the DVVC especially advantageous when used at the secondary side of an IPT system. Moreover, since the equivalent capacitance of the DVVC can be controlled smoothly with a DC voltage and the passive diode generates less EMI than active switches, the DVVC has the potential to be used at much higher frequencies than traditional switch mode capacitors.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.326-329
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• 2002

In this paper, we investigated a feasibility of cerium oxide(CeO$_2$) films as a buffer layer of MFIS(metal ferroelectric insulator semiconductor) type capacitor. CeO$_2$ layer were Prepared by two step process of a low temperature film growth and subsequent RTA (rapid thermal annealing) treatment. By app1ying an ultra thin Ce metal seed layer and N$_2$ Plasma treatment, dielectric and interface properties were improved. It means that unwanted SiO$_2$ layer generation was successfully suppressed at the interface between He buffer layer and Si substrate. The lowest lattice mismatch of CeO$_2$ film was as low as 1.76% and average surface roughness was less than 0.7 m. The Al/CeO$_2$/Si structure shows breakdown electric field of 1.2 MV/cm, dielectric constant of more than 15.1 and interface state densities as low as 1.84${\times}$10$\^$11/ cm$\^$-1/eV$\^$-1/. After N$_2$ plasma treatment, the leakage current was reduced with about 2-order.