• Journal of Digital Contents Society
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• v.8 no.3
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• pp.279-288
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• 2007

Recently, Baruah et. al. proposed an optimal Pfair scheduling algorithm in the real-time multiprocessor system environments, and several variants of it were presented. All these algorithms assume the fixed unit quantum size. However, under Pfair based scheduling algorithms that are global scheduling technique, quantum size has direct influence on the scheduling overheads such as task switching and cache reload. We proposed a method for deciding the optimal quantum size[2] and an improved method for the task set whose utilization e is less than or equal to $e\;{\leq}\;p/3+1$[3]. However, these methods use repetitive computation of the task's utilization to determine the optimal quantum size. In this paper, we propose a more efficient method that can determine the optimal quantum size in constant time.

• The Transactions of the Korea Information Processing Society
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• v.6 no.10
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• pp.2764-2771
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• 1999

ATM has recently received much attention because of its high capacity, its bandwidth scalability, and its ability to support multiservice traffic. However, ATM is connection oriented whereas the vast majority of modern data networking protocols are connectionless. The alternative to support current service on ATM will be a router with attached switching hardware that has the ability to cache routing decisions. In this paper, we described the router using a switch and simulated the performance. From the results of the simulation, the routing delay was decreased as the number of flow channels. Cell-delay was shortest at 30,000 cell-time when the keeping time of a flow channel was. The line utilization was rapidly decrease when a flow-setup time is 20 30 cell-time. The results of this simulation could be applied to predict the performance of the router using ATM switch.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.2
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• pp.514-535
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• 2019

Information-centric networks operate under the assumption that all network components have built-in caching capabilities. Integrating the caching strategies of information centric networking (ICN) with wireless virtualization improves the gain of virtual infrastructure content caching. In this paper, we propose a framework for software-defined information centric virtualized wireless device-to-device (D2D) networks. Enabling D2D communications in virtualized ICN increases the spectral efficiency due to reuse and proximity gains while the software-defined network (SDN) as a platform also simplifies the computational overhead. In this framework, we propose a joint virtual resource and cache allocation solution for latency-sensitive applications in the next-generation cellular networks. As the formulated problem is NP-hard, we design low-complexity heuristic algorithms which are intuitive and efficient. In our proposed framework, different services can share a pool of infrastructure items. We evaluate our proposed framework and algorithm through extensive simulations. The results demonstrate significant improvements in terms of visiting latency, end user QoE, InP resource utilization and MVNO utility gain.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.12
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• pp.968-972
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• 2009

The multi-core processors are being widely exploited by many high-end systems. With significant advances in processor architecture, the network band-width required on the high-end systems is increasing drastically. It is therefore highly desirable to manage multiple cores efficiently to achieve high network band-width with minimum resource requirements. Modern operating systems, however, still have significant design and optimization space to leverage the network performance over multi-core systems. In this paper, we suggest a novel networking process scheduling scheme, which decides the best processor affinity of networking processes based on the processor cache layout, communication intensiveness, and processor loads. The experimental results show that the scheduling scheme implemented in the Linux kernel can improve the network bandwidth and the effectiveness of processor utilization by 20% and 59%, respectively.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.9
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• pp.1073-1082
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• 1999

본 논문에서는 시스템 내의 프로세서들을 효과적으로 사용하기 위한 적응적 프로세서 할당 정책을 제안한다. 프로그램의 병렬성을 향상시키기 위하여 일반적으로 병렬 처리에 사용될 프로세서 개수를 증가시킨다. 그러나 증가된 프로세서들은 그레인 크기에 변화를 일으키며 이는 캐쉬 성능에 영향을 미친다. 특히 대역이 제한된 공유 버스를 사용하는 시스템에서는 프로세서 개수의 증가는 공유 버스에 대한 접근 경쟁을 크게 증가하므로 버스에서 대기하는 시간이 프로세서 증가에 의한 계산 능력 이득을 상쇄시키는 주요한 원인이 되고 있다. 본 논문에서 제안한 적응적 프로세서 할당 정책은 프로그램이 수행되는 도중에 임의의 기간동안 공유버스에 대기중인 프로세서 분포에 관한 정보를 얻는다. 그리고 이 정보를 바탕으로 프로세서 개수를 변경하는 방법이다. 모의 시험에서 적응적 프로세서 할당 정책은 프로그램들의 버스 트래픽 특성에 따른 최적의 적합한 프로세서 개수를 발견함을 보인다. 그리고 적응적 프로세서 할당 정책은 고정된 프로세서 개수를 사용한 가장 좋은 성능보다는 다소 떨어진 성능을 나타내었으나 시스템의 프로세서 활용성을 높여 효과적 시스템 사용에 기여함을 보인다. Abstract In this paper, the adaptive processor allocation policy is suggested to make effective use of processors in system. To enhance the parallelism, the number of processors used in the parallel computing may be increased. However, increasing the number of processors affects the grain size of the parallel program. Therefore, it affects the cache performance. In particular, when the shared bus is employed, since increasing the number of processors can result in a significant amount of contention to achieve the shared-bus, the increased computing power is offset by the bus waiting time due to these contentions. The adaptive processor allocation policy acquires the information about the distribution of waiting processors on shared bus for any execution period of programs. And it changes the number of processors working in parallel processing during the program's run. Our simulation results show that the adaptive processor allocation policy finds the optimum feasible number of processors based on the bus traffic characteristic of programs. Thus, it contributes to effective system utilization, even though it performs slightly less efficiently than using a fixed number of processors with the best performance.

• KIISE Transactions on Computing Practices
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• v.22 no.9
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• pp.473-478
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• 2016

Server virtualization provides abstraction of physical resources to users and thus accomplishes high resource utilization and flexibility. However, the characteristics of server virtualization, such as the limited number of physical resources shared by virtual machines, can cause problems, mainly performance interference. The performance interference is caused by the fact that the CPU scheduler running on the host operating system schedules virtual machines without considering the characteristics of the virtual machine's internal process. To address performance interference, a number of research activities to improve performance interference have been conducted, but do not deal with the fundamental analysis of performance interference. In this paper, in order to analyze the cause of performance interference, we carry out profiling in a variety of scenarios in a virtualized environment based on KVM. As a result, we analyze the phenomenon of the performance interference in terms of CPU scheduling and propose an efficient scheduling solution.

• Journal of the Korea Computer Graphics Society
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• v.23 no.2
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• pp.1-10
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• 2017

A variety of filters are applied to improve the quality of noise and low resolution medical images. This is necessary to reduce the radiation dose of the patient and to improve the utilization of the conventional spherical imaging equipment. In the conventional method, it is common to perform filtering using the CPU of the PC. However, it is difficult to produce results in real time by applying various calculations and filters to high-resolution human images using only the CPU performance of a PC used in a hospital. In this paper, we analyze the structure and performance of Intel integrated GPU in CPU and propose a method to perform image filtering using OpenCL parallel processing function. By applying complex filters with high computational complexity to medical images, high quality images can be generated in real time.

• Journal of KIISE:Computing Practices and Letters
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• v.5 no.6
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• pp.700-707
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• 1999

본 논문에서는 GIS 관련 연산을 실시간에 효율적으로 처리하기 위한 분산공유메모리 기반 병렬처리 시스템을 제안한다. 본 논문의 분산공유메모리 시스템은 메시지전달 방식의 분산메모리 MIMD 컴퓨터 상에 소프트웨어 기반 분산공유메모리 모듈을 탑재함으로써 구현되었다. 또한 GIS 연산의 기본이 되는 공간 객체를 공유의 기본 단위로 설정하고, GIS 데이타의 특성을 반영하여 읽기전용 공유데이타 타입을 추가하였으며, 네트워크 오버헤드를 줄이기 위하여 복수의 객체를 한번에 읽어오는 bulk access가 가능하도록 하였다. 본 시스템에서는 GIS 데이타의 효율적인 분배를 위하여 부하균등화 기법으로 guided self scheduling을 사용하였다. 실험결과 본 시스템은 네트워크 캐쉬의 효율적인 활용을 통하여 소프트웨어 기반 분산메모리 시스템의 오버헤드에도 불구하고 MPI 기반 메시지전달 방식에 비하여 향상된 성능을 얻을 수 있었다.Abstract In this paper, we propose a distributed shared memory(DSM) based parallel processing system to process GIS related computations efficiently in real time. The system is based on a software DSM module implemented on top of a distributed MIMD computer. In the DSM system, spatial object, which is a fundamental structure to represent GIS data, is used as a basic unit for sharing, and a read-only shared data type is added to reflect the characteristics of GIS data. In addition, a bulk access to multiple shared data is made possible to reduce the network overhead. A guided self scheduling method is devised for efficient load balancing in distributing GIS data to parallel processors. The experimental results show that the DSM system performs better than an MPI based message-passing system through the efficient utilization of network cache in spite of the system's software overhead.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.15 no.7
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• pp.2496-2512
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• 2021

The requirements for powerful computing capability, high capacity, low latency and low energy consumption of emerging services, pose severe challenges to the fifth-generation (5G) network. As a promising paradigm, mobile edge networks can provide services in proximity to users by deploying computing components and cache at the edge, which can effectively decrease service delay. However, the coexistence of heterogeneous services and the sharing of limited resources lead to the competition between various services for multiple resources. This paper considers two typical heterogeneous services: computing services and content delivery services, in order to properly configure resources, it is crucial to develop an effective offloading and caching strategies. Considering the high energy consumption of 5G base stations, this paper considers the hybrid energy supply model of traditional power grid and green energy. Therefore, it is necessary to design a reasonable association mechanism which can allocate more service load to base stations rich in green energy to improve the utilization of green energy. This paper formed the joint optimization problem of computing offloading, caching and resource allocation for heterogeneous services with the objective of minimizing the on-grid power consumption under the constraints of limited resources and QoS guarantee. Since the joint optimization problem is a mixed integer nonlinear programming problem that is impossible to solve, this paper uses deep reinforcement learning method to learn the optimal strategy through a lot of training. Extensive simulation experiments show that compared with other schemes, the proposed scheme can allocate resources to heterogeneous service according to the green energy distribution which can effectively reduce the traditional energy consumption.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.11
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• pp.45-52
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• 1994

In recent days low cost, high performance microprocessors have led to construction of medium scale shared memory multiprocessor systems with shared bus. Such multiprocessor systems are heavily influenced by the structures of memory systems and memory systems become more important factor in design space as microprocessors are getting faster. Even though local cache memories are very common for such systems, the latency on access to the shared memory limits throughput and scalability. There have been many researches on the memory structure for multiprocessor systems. In this paper, an asynchronous memory architecture is proposed to utilize the bandwith of system bus effectively as well as to provide flexibility of implementation. The effect of the proposed architecture if shown by simulation. We choose, as our model of the shared bus is HiPi+Bus which is designed by ETRI to meet the requirements of the High-Speed Midrange Computer System. The simulation is done by using Verilog hardware decription language. With this simulation, it is explored that the proposed asynchronous memory architecture keeps the utilization of system bus low enough to provide better throughput and scalibility. The implementation trade-offs are also described in this paper. The asynchronous memory is implemented and tested under the prototype testing environment by using test program. This intensive test has validated the operation of the proposed architecture.