• Journal of KIISE:Computer Systems and Theory
• /
• v.31 no.8
• /
• pp.473-486
• /
• 2004

NUMA systems have remote access caches(RAC) in each local node to reduce the overhead for repeated remote memory accesses. By this RAC, memory latency and network traffic can be reduced and the performance of the multiprocessor system can be improved. Until now, several cache replacement policies have been proposed in recent years, and there also is cache replacement policy for multiprocessor systems. In this paper, we propose a cache replacement policy which is based on cache line coherence information. In this policy, the cache line that does not have an ownership is replaced first with respect to cache line that has an ownership. Like this way, the overhead to transfer ownership is avoided and the memory latency can be decreased. We also propose “Keeping-Ownership replacement policy with MRU (KOM)” and “Keeping-Ownership replacement policy with Reference Bit(KORB)” to reduce the frequent replacement penalty of the ownership-lacking cache line. We compare and analyze these with LRU and Pseudo LRU(PLRU). The simulation shows that KOM outperforms the PLRU by 25%, and KORB outperforms the PLRU by 13%. Although the hardware cost of KOM is very small, the performance of KOM is nearly equal to that of the LRU.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.19 no.7
• /
• pp.1282-1295
• /
• 1994

In this paper, a hierarchical cluster multiprocessor system based on a hierarchical bus system is proposed and its cache coherency protocol is designed and implemented. The hierarchical cluster architecture aims at elimination the system bottleneck of the existing single bus system by adding a hierarchy of buses as the number of clusters is increased. Therefore the system is easy to scale up to a large number of processors. The proposed cache protocol is designed to be adapted to the general N-level (N>2) hierarchical cluster architecture. The original pended protocol is extended to implement the cache protocol on the system bus and cache coherency operations for this protocol are explained.

• The Transactions of the Korean Institute of Electrical Engineers D
• /
• v.54 no.10
• /
• pp.615-619
• /
• 2005

Token coherence protocol has many good reasons against snooping/directory-based protocol in terms of latency, bandwidth, and complexity. Token counting easily maintains correctness of the protocol without global ordering of request which is basis of other dominant cache coherence protocols. But this lack of global ordering causes starvation which is not happening in snooping/directory-based protocols. Token coherence protocol solves this problem by providing an emergency mechanism called persistent request. It enforces other processors in the competition (or accessing same shared memory block, to give up their tokens to feed a starving processor. However, as the number of processors grows in a system, the frequency of starvation occurrence increases. In other words, the situation where persistent request occurs becomes too frequent to be emergent. As the frequency of persistent requests increases, not only the cost of each persistent matters since it is based on broadcasting to all processors, but also the increased traffic of persistent requests will saturate the bandwidth of multiprocessor interconnection network. This paper proposes a new request mechanism that defines order of requests to reduce occurrence of persistent requests. This ordering mechanism has been designed to be decentralized since centralized mechanism in both snooping-based protocol and directory-based protocol is one of primary reasons why token coherence protocol has advantage in terms of latency and bandwidth against these two dominant Protocols.

• Proceedings of the Korean Information Science Society Conference
• /
• 2008.06a
• /
• pp.303-304
• /
• 2008

• The Transactions of the Korea Information Processing Society
• /
• v.7 no.12
• /
• pp.3964-3975
• /
• 2000

There are two policies for maintaining consistency among the multiple processor caches in a multiprocessor system: Write invalidate and Write update. In the write invalidate policy, whenever a processor attempt to write its cached block, it has to invalidate all the same copies of the updated block in the system. As a results of this frequent invalidations, this policy results in high cache miss ratio. On the other hand, the write update policy renew them, instead of invalidating all the same copies. This policy has to transfer the updated contents through interconnection network, whether the updated block is ptivate or not. Therefore the network suffer from heavy transaction traffic. In this paper we present an efficient cache coherence protocol for shared memory multiprocessor system connected by slotted ring. This protocol is based on the write update policy, but the updated contents are transferred only in case of updating the shared block. Otherwise, if the updated block is private, the updated contents are not transferred. We analyze the proposed protocol and enforce simulation to compare it with previous version.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.39 no.3
• /
• pp.1-17
• /
• 2002

In this paper, we present our experiences in using symbolic model checker(SMV) to analyze a number of properties of RACE cache coherence protocol designed by ETRI(Electronics and Communications Research Institute) and to verify that RACE protocol satisfies important requirements. To investigate this, we specified the model of the RACE protocol as the input language of SMV and specified properties as a formula in temporal logic CTL. We successfully used the symbolic model checker to analyze a number of properties of RACE protocol. We verified that abnormal state/input combinations was not occurred and every possible request of processors was executed correctly We verified that RACE protocol satisfies liveness, safety and the property that any abnormal state/input combination was never occurred. Besides, We found some ambiguities of the specification and a case of starvation that the protocol designers could not expect before. By this verification experience, we show advantages of model checking method. And, we propose a new method to generate automatically test cases which are used in simulation and testing.

• Proceedings of the Korean Information Science Society Conference
• /
• 1999.10c
• /
• pp.6-8
• /
• 1999

세그먼트 디렉토리는 CC-NUMA (Cache Coherent Non-Uniform Memory Access)시스템의 전체 벡터와 포인터의 장점만을 가지는 새로운 형태의 디렉토리 요소이다. 포인터가 하나의 프로세서 위치만을 가리키는데 비해, 세그먼트 디렉토리는 복수 개이 프로세서들을 한 번에 가리킬 수 있으면서, 포인터처럼 작은 단위로 사용가능하다. 본 논문에서는 세그먼트 디렉토리를 제한 디렉토리 방법들에 적용하여 디렉토리 넘침의 횟수를 줄인다. 기존의 방법들이 디렉토리 넘침 후의 효율적인 캐쉬 일관성 유지 기법을 제시했던 것에 비해, 세그먼트 디렉토리는 디렉토리 넘침 자체를 제거하는 최초의 시도이다. 디렉토리 넘침의 제거로 CC-NUMA 시스템 대역폭 요구량이 줄어들고, 프로그램 수행이 가속되며, 디렉토리 제어기 점유가 대폭 감소된다. Tango-Lite를 사용한 실행 구동 시뮬레이션을 통하여 세그먼트 디렉토리가 약 80%까지의 디렉토리 넘침을 제거한 것을 확인하였고, 이에 따르는 시스템 성능 향상을 분석하였다.

• Journal of the Korea Society of Computer and Information
• /
• v.8 no.1
• /
• pp.51-59
• /
• 2003

It is effective to be located in the double nodes in the distributed object replication systems, then object which nodes share is the same contents. The nodes store an access information on their local cache as it access to the system. and then the nodes fetch and use it, when it needed. But with time the coherence Problems will happen because a data carl be updated by other nodes. So keeping the coherence of the system we need a mechanism that we managed the to improve to improve the performance and availability of the system effectively. In this paper to keep coherence in the shared memory condition, we can set the limited parallel performance without the additional cost except the coherence cost using it to keep the object at the proposed adaptive duplication object(ADO) algorithms. Also to minimize the coherence maintenance cost which is the bi99est overhead in the duplication method, we must manage the object effectively for the number of replication and location of the object replica which is the most important points, and then it determines the cos. And that we must study the adaptive duplication object management mechanism which will improve the entire run time.

• Proceedings of the Korean Information Science Society Conference
• /
• 2002.04a
• /
• pp.604-606
• /
• 2002

기존의 디렉토리 프로토콜은 독점 상태 데이터의 읽기 과정에서 홈 노드 갱신을 수행한다. 한편 이주 데이터는 한 프로세서에 의해 읽힌 뒤 곧이어 수정되므로 그와 같은 홈 노드 갱신이 전혀 쓸모없게 된다. 본 논문에서는 기존의 디렉토리 캐쉬 일관성 기법을 수정하여 이주 데이터에 대해 발생하는 불필요한 홈 노드 갱신을 줄이는 개선된 기법을 제안한다. 제안된 기법은 시주 데이터의 빈도가 높은 병렬 프로그램에서 캐쉬 일관성 트래픽을 크게 감소시켰고 이는 자연히 네트웍 지연 시간의 단축을 가져왔다.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2007.05a
• /
• pp.1447-1449
• /
• 2007

본 논문은 이동 컴퓨팅 환경에서 시간 주기적인 인간의 행동 패턴에 따른 캐쉬 일관성 기법을 제안하고자 한다. 행동 유형 모델을 근거로 하여 시간 주기적인 행동의 패턴과 이동 기기의 사용 패턴이 동일 또는 흡사함을 가정한다. 이를 통해 패턴 예측 테이블을 구성하고, 시간대별로 구성된 테이블의 예측 데이터를 사용하여 서버와의 통신할 때 지연 현상을 방지 하는 기법을 제안한다.