• 한국컴퓨터정보학회논문지
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• 제20권9호
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• pp.1-10
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• 2015

In this paper, we propose a new variable latency L1 data cache architecture for multi-core processors. Our proposed architecture extends the traditional variable latency cache to be geared toward the multi-core processors. We added a specialized data structure for recording the latency of the L1 data cache. Depending on the added latency to the L1 data cache, the value stored to the data structure is determined. It also tracks the remaining cycles of the L1 data cache which notifies data arrival to the reservation station in the core. As in the variable latency cache of the single-core architecture, our proposed architecture flexibly extends the cache access cycles considering process variation. The proposed cache architecture can reduce yield losses incurred by L1 cache access time failures to nearly 0%. Moreover, we quantitatively evaluate performance, power, energy consumption, power-delay product, and energy-delay product when increasing the number of cache access cycles.

• Journal of Communications and Networks
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• 제17권1호
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• pp.40-46
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• 2015

In a mobile ad hoc network (MANET), communication between mobile nodes occurs without centralized control. In this environment the mobility of a node is unpredictable; this is considered as a characteristic of wireless networks. Because of faulty or malicious nodes, the network is vulnerable to routing misbehavior. The resource constrained characteristics of MANETs leads to increased query delay at the time of data access. In this paper, AntHocNet+ Security (ANTSEC) framework is proposed that includes an enhanced cooperative caching scheme embedded with artificial immune system. This framework improves security by injecting immunity into the data packets, improves the packet delivery ratio and reduces end-to-end delay using cross layer design. The issues of node failure and node malfunction are addressed in the cache management.