• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2018.06a
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• pp.140-140
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• 2018

The 3D interconnect technologies have been appeared, as the density of Integrated Circuit (IC) devices increases. Through Silicon Via (TSV) process is an important technology in the 3D interconnect technologies. And the process is used to form a vertically electrical connection through silicon dies. This TSV process has some advantages that short length of interconnection, high interconnection density, low electrical resistance, and low power consumption. Because of these advantages, TSVs could improve the device performance higher. The fabrication process of TSV has several steps such as TSV etching, insulator deposition, seed layer deposition, metallization, planarization, and assembly. Among them, TSV metallization (i.e. TSV filling) was core process in the fabrication process of TSV because TSV metallization determines the performance and reliability of the TSV interconnect. TSVs were commonly filled with metals by using the simple electrochemical deposition method. However, since the aspect ratio of TSVs was become a higher, it was easy to occur voids and copper filling of TSVs became more difficult. Using some additives like an accelerator, suppressor and leveler for the void-free filling of TSVs, deposition rate of bottom could be fast whereas deposition of side walls could be inhibited. The suppressor was adsorbed surface of via easily because of its higher molecular weight than the accelerator. However, for high aspect ratio TSV fillers, the growth of the top of via can be accelerated because the suppressor is replaced by an accelerator. The substitution of the accelerator and the suppressor caused the side wall growth and defect generation. The suppressor was used as Single additive electrodeposition of TSV to overcome the constraints. At the electrochemical deposition of high aspect ratio of TSVs, the suppressor as single additive could effectively suppress the growth of the top surface and the void-free bottom-up filling became possible. Generally, copper was used to fill TSVs since its low resistivity could reduce the RC delay of the interconnection. However, because of the large Coefficients of Thermal Expansion (CTE) mismatch between silicon and copper, stress was induced to the silicon around the TSVs at the annealing process. The Keep Out Zone (KOZ), the stressed area in the silicon, could affect carrier mobility and could cause degradation of the device performance. Cobalt can be used as an alternative material because the CTE of cobalt was lower than that of copper. Therefore, using cobalt could reduce KOZ and improve device performance. In this study, high-aspect ratio TSVs were filled with cobalt using the electrochemical deposition. And the filling performance was enhanced by using the suppressor as single additive. Electrochemical analysis explains the effect of suppressor in the cobalt filling bath and the effect of filling behavior at condition such as current type was investigated.

• Korean Journal of Materials Research
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• v.8 no.8
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• pp.744-750
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• 1998

Unlike common device, MEMS(micro-electro-mechanical system) device consists of very small mechanical structures which determine the performance of the device. Because of its small mechanical structure inside. MEMS device is very sensitive to thermal stress caused by CTE(coefficient of thermal expansion) mismatch between its components. Therefore, its characteristics are affected by material properties. process temperature. and dimensions of each layer such as chip, adhesive and substrate. In this study. we investigated the change of the thermal stress in the chip attached to a substrate. With computer-aided finite element method (FEM), the computer simulation of the thermal stress was conducted on variables such as bonding material, process temperature, bonding layer thickness and die size. The commercial simulation program, ABAQUS ver5.6, was used. Subsequently 3-layer test samples were fabricated, and their degree of bending were measured by 3-D coordinate measuring machine. The experimental results were in good agreement with the simulation results. This study shows that the bonding layer could be the source of stress or act as the buffer layer for stress according to its elastic modulus and CTE. Solder adhesive layer was the source of stress due to its high elastic modulus, therefore high compressive stress was developed in the chip. And the maximum tensile stress was developed in the adhesive layer. On the other hand, polymer adhesive layer with low elastic modulus acted as buffer layer, and resulted in lower compressive stress. The maximum tensile stress was developed in the substrate.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.36 no.2
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• pp.187-194
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• 2012

The strength of particle-reinforced metal matrix composites is, in general, known to be increased by the geometrically necessary dislocations punched around a particle that form during cooling after consolidation because of coefficient of thermal expansion (CTE) mismatch between the particle and the matrix. An additional strength increase may also be observed, since another type of geometrically necessary dislocation can be formed during extensive deformation as a result of the strain gradient plasticity due to the elastic-plastic mismatch between the particle and the matrix. In this paper, the magnitudes of these two types of dislocations are calculated based on the dislocation plasticity. The dislocations are then converted to the respective strengths and allocated hierarchically to the matrix around the particle in the axisymmetric finite-element unit cell model. The proposed method is shown to be very effective by performing finite-element strength analysis of $SiC_p$/Al2124-T4 composites that included ductile failure in the matrix and particlematrix decohesion. The predicted results for different particle sizes and volume fractions show that the length scale effect of the particle size obviously affects the strength and failure behavior of the particle-reinforced metal matrix composites.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.112-112
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• 2009

In this study, the effect of a long post-deposition thermal annealing(600 and 1000 $^{\circ}C$) on the surface acoustic wave (SAW) properties of polycrystalline (poly) aluminum-nitride (AlN) thin films grown on a 3C-SiC buffer layer was investigates. The poly-AlN thin films with a (0002) preferred orientation were deposited on the substrates by using a pulsed reactive magnetron sputtering system. Experimental results show that the texture degree of AlN thin film was reduced along the increase in annealing temperature, which caused the decrease in the electromechanical coupling coefficient ($k^2$). The SAW velocity also was decreased slightly by the increase in root mean square (RMS) roughness over annealing temperature. However, the residual stress in films almost was not affect by thermal annealing process due to small lattice mismatch different and similar coefficient temperature expansion (CTE) between AlN and 3C-SiC. After the AlN film annealed at 1000 $^{\circ}C$, the insertion loss of an $IDT/AlN/3C-SiC/SiO_2/Si$ structure (-16.44 dB) was reduced by 8.79 dB in comparison with that of the as-deposited film (-25.23 dB). The improvement in the insertion loss of the film was fined according to the decrease in the grain size. The characteristics of AlN thin films were also evaluated using Fourier transform-infrared spectroscopy (FT-IR) spectra and X-ray diffraction (XRD), scanning electron microscopy (SEM), and atomic force microscopy (AFM) images.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.235-235
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• 2009

This paper describes the influence of a polycrystalline (poly) 3C-SiC buffer layer on the surface acoustic wave (SAW) properties of poly aluminum nitride (AlN) thin films by comparing the center frequency, insertion loss, the electromechanical coupling coefficient ($k^2$), andthetemperaturecoefficientoffrequency(TCF) of an IDT/AlN/3C-SiC structure with those of an IDT/AlN/Si structure, The poly-AlN thin films with an (0002)-preferred orientation were deposited on a silicon (Si) substrate using a pulsed reactive magnetron sputtering system. Results show that the insertion loss (21.92 dB) and TCF (-18 ppm/$^{\circ}C$) of the IDT/AlN/3C-SiC structure were improved by a closely matched coefficient of thermal expansion (CTE) and small lattice mismatch (1 %) between the AlN and 3C-SiC. However, a drawback is that the $k^2(0.79%)$ and SAW velocity(5020m/s) of the AlN/3C-SiC SAW device were reduced by appearing in some non-(0002)AlN planes such as the (10 $\bar{1}$ 2) and (10 $\bar{1}$ 3) AlN planes in the AlN/SiC film. Although disadvantages were shown to exist, the use of the AlN/3C-SiC structure for SAW applications at high temperatures is possible. The characteristics of the AlN thin films were also evaluated using FT-IR spectra, XRD, and AFM images.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.4
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• pp.85-90
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• 2011

With regard to reliability of solder joint, the significant failures include open defects that occurs from alignment problem, Head in Pillow by PCB's warpage, the crack of solder by CTE mismatch, and the crack of IMC layer by mechanical impact. Especially as PCB down-sizing and surface finish is under progress, brittle failure of IMC layer between solder bump and PCB pad becomes a big issue. Therefore, it requires enhancing the level of difficulty in the existing assessment method and improving the measurement through the study on the mechanism of IMC formation, growth and brittle failure. Under this circumstance, this study is intended to suggest the direction of research for improving the reliability on the crack such as improvement of IMC brittle fracture.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.35 no.7
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• pp.745-751
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• 2011

This study proposes finite element modeling of dislocation punching at cooling after consolidation in order to calculate the strength of particle-reinforced aluminum composites. The Taylor dislocation model combined with strain gradient plasticity around the reinforced particle is adopted to take into account the size-dependency of different volume fractions of the particle. The strain gradients were obtained from the equivalent plastic strain calculated during the cooling of the spherical unit cell, when the dislocation punching due to CTE (Coefficient of Thermal Expansion) mismatch is activated. The enhanced yield stress was observed by including the strain gradients, in an average sense, over the punched zone. The tensile strength of the SiCp/Al 356-T6 composite was predicted through the finite element analysis of an axisymmetric unit cell for various sizes and volume fractions of the particle. The predicted strengths were found to be in good agreement with the experimental data. Further, the particle-size dependency was clearly established.

• Journal of the Korean Ceramic Society
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• v.51 no.3
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• pp.170-176
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• 2014

Effective glass frit compositions enabled to absorb laser energy, and to seal a commercial dye-sensitized solar-cell-panel substrate were developed by using $V_2O_5$-based glasses with various amounts of $TeO_2$ substitution. The latter was intended to increase the lifetime of the solar cells. Substitution of $V_2O_5$ by $TeO_2$ provided a strong network structure for the glasses via the formation of tetrahedral pyramids in the glass, and changed the various glass properties, such as glass transition temperature ($T_g$), dilatometric softening point ($T_d$), crystallization temperature, coefficient of thermal expansion (CTE), and glass flowage without any detrimental effect on the laser absorption property of the glasses. The thermal expansion mismatch (${\Delta}{\alpha}$) between the glass frit and the substrate could be controlled within less than ${\pm}5%$ by addition of 10 wt% of ${\beta}$-eucryptite. An 810 nm diode laser was used for the sealing test. The laser sealing test revealed that the VZBT20 glass frit with 10 wt% ${\beta}$-eucryptite was successfully sealed the substrates without interfacial cracks and pores. The optimum sealing conditions were provided by a beam size of 3 mm, laser power of 40 watt, scan speed of 300 mm/s, and 200 irradiation cycles.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.38 no.5
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• pp.483-487
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• 2014

In this study, joining methods with SiC powder as the joining adhesives were studied in order to avoid the residual stresses coming from CTE (Coefficient of Thermal Expansion) mismatch between substrate and joining layer. The shear strength and microstructure of joined material between SiC substrates are investigated. The commercial Hexoloy-SA (Saint-Gobain Ceramics, USA) used in this work as substrate material. The fine ${\beta}$-SiC nano-powder which the average particle size is below 30 nm, $Al_2O_3$, $Y_2O_3$, and $SiO_2$ were used as joining adhesives. The specimens were joined with 20MPa and $1400-1900^{\circ}C$ by hot pressing in argon atmosphere. The shear test was performed to investigate the bonding strength. The cross-section of the joint was characterized by using an optical microscope and scanning electron microscopy (SEM).

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.251-254
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• 2007

Principal challenges to $\underline{direct\;fabrication}$ of high performance a-Si:H transistor arrays on flexible substrates include automated handling through bonding-debonding processes, substrate-compatible low temperature fabrication processes, management of dimensional instability of plastic substrates, and planarization and management of CTE mismatch for stainless steel foils. Viable solutions to address these challenges are described.