• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.12
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• pp.2839-2846
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• 2014

New VHF band for use in VDE is determined by WRC-12 due to the overload of AIS VDL, and the system characteristics of the VDE is recommended as ITU-R M. 1842-1. CS-TDMA, a multiple access method of AIS class B, is recommended as that of the VDE. It is inefficient for CS-TDMA just applying the report interval used in AIS class B to transmit high speed data with higher payload in the aspect of efficiency. In this paper, a simulation is executed in order to determine adequate report interval according to the number of active ships that affects directly network traffic. To this end, the performance of CS-TDMA, which includes the number of received packets, reception success rate, channel utilization, and collision rate, is investigated via a simulation.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.4
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• pp.13-24
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• 2002

CDMA 시스템은 성능의 우수성에도 불구하고 신호처리의 복잡성과, 여러 채널의 신호를 동시에 전송시, 채널수가 증가할수록 신호의 PAPR(Peak to Average Power Ratio)가 증가하는 문제점을 갖고 있다. 본 논문에서는 멀티코드 CDMA의 특성과 구조를 유지하면서도 전송신호의 레벨이 항상 일정하여 기존의 TDMA 시스템 구조로도 멀티코드 CDMA 신호를 전송할 수 있는 Binary CDMA 기술에 대해 소개한다. Binary CDMA 기술은 적용 기술별로는 펄스폭 CDMA(PW/CDMA; Pulse Width CDMA), 다위상 CDMA(MP/CDMA; Multi Phase CDMA), 코드선택 CDMA(CS/CDMA; Code Select CDMA)로 구분되며, 사용자간의 상호간섭이 심한 환경에서 무선으로 실시간 멀티미디어를 보내는 소형 휴대형 장비에 적합한 무선 solution을 제공한다.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.5
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• pp.1-7
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• 2008

The general bus architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. Specially, as several masters do not concurrently receive the right of bus usage, the arbiter plays an important role in arbitrating between shared bus and masters. Fixed priority, round-robin, TDMA and Lottery methods are developed in general arbitration policies, which lead the efficiency of bus usage in shared bus. On the other hand, the bus architecture can be modified to maximize the system performance. In the paper, we propose the flying master bus architecture that supports the parallel bus communication and analyze its merits and demerits following various arbitration policies that are mentioned above, compared with normal shared bus. From the results of performance verification using TLM(Transaction Level Model), we find that more than 40% of the data communication performance improves, regardless of arbitration policies. As the flying master bus architecture advances its studies and applies various SoCs, it becomes the leading candidate of the high performance bus architecture.