• Journal of the Semiconductor & Display Technology
• /
• v.10 no.4
• /
• pp.7-13
• /
• 2011

In this paper, the IC(Integrated Circuit) for multi-channel synchronous communication was designed by using FPGA and VHDL language. The existing chips for synchronous communication that has been used commercially are composed for one to two channels. Therefore, when communication system with three channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 synchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 1024 bytes respectively and consequently high speed communication became possible. It was designed with a communication signal of a form various encoding. To detect errors of communications, the CRC-ITU-T logic and channel MUX logic was designed with hardware logics so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. In order to show the performance of designed IC, the test was conducted successfully in Quartus simulation and experiment and the excellence was compared with the 85C3016VSC of ZILOG company that are used widely as chips for synchronous communication.

• Journal of the Semiconductor & Display Technology
• /
• v.10 no.3
• /
• pp.1-6
• /
• 2011

In this paper, the IC(Integrated Circuit) for multi-channel synchronous communication was designed by using FPGA and VHDL language. The existing chips for synchronous communication that has been used commercially are composed for one to two channels. Therefore, when communication system with three channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 synchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 1024 bytes respectively and consequently high speed communication became possible. It was designed with a communication signal of a form various encoding. To detect errors of communications, the CRC-ITU-T logic and channel MUX logic was designed with hardware logics so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. In order to show the performance of designed IC, the test was conducted successfully in Quartus simulation and experiment and the excellence was compared with the 85C3016VSC of ZILOG company that are used widely as chips for synchronous communication.

• Annual Conference of KIPS
• /
• 2001.10b
• /
• pp.1379-1382
• /
• 2001

본 논문에서는 ATM 망에서의 통합 네트워크 구현을 위한 IP data packet를 처리하기 위한 AAL type5 프로토콜 프로세서를 설계 및 구현하였다. AAL 계층의 중요 기능들은 ITU-T Recommendation 1.363과 1.363.5 에 근거하여 설계하였다. AAL 계층의 주요한 역할은 데이터의 Segmentation 및 셀의 Reassembly를 하는 것으로, Segmentation 과정에서는 상위 계층의 연속적인 데이터를 Segmentation하여 53-byte 크기의 ATM 셀을 구성하는 기능이다. Reassembly 과정에서는 들어오는 셀들을 연속적인 데이터로 만들어 AAL 계층 보다 상위 계층으로 전달하는 것이다. 이 과정에서 셀의 Header 를 확인한 후 crc-32를 통한 오류 검정을 거치게 되며, 데이터에 오류가 있을 경우에는 해당 셀을 버리고 오류가 없을 시에만 상위 계층으로 전달한다. 본 논문에서 구현한 AAL Type 5 프로세서는 향후 모든 Type의 data를 수용하는 칩 개발에 유용할 것으로 사료된다. 본 논문에서 원할한 테스트를 위해 데이터의 loop back 신호 DLB를 사용했다 VHDL 해석기로는 Synopsys 사의 VHDL Analyzer를 사용하였고, Design Compiler로 회로를 합성하였다.