• Title/Summary/Keyword: CPU 시간

Search Result 518, Processing Time 0.029 seconds

Real-time Color Recognition Based on Graphic Hardware Acceleration (그래픽 하드웨어 가속을 이용한 실시간 색상 인식)

  • Kim, Ku-Jin;Yoon, Ji-Young;Choi, Yoo-Joo
    • Journal of KIISE:Computing Practices and Letters
    • /
    • v.14 no.1
    • /
    • pp.1-12
    • /
    • 2008
  • In this paper, we present a real-time algorithm for recognizing the vehicle color from the indoor and outdoor vehicle images based on GPU (Graphics Processing Unit) acceleration. In the preprocessing step, we construct feature victors from the sample vehicle images with different colors. Then, we combine the feature vectors for each color and store them as a reference texture that would be used in the GPU. Given an input vehicle image, the CPU constructs its feature Hector, and then the GPU compares it with the sample feature vectors in the reference texture. The similarities between the input feature vector and the sample feature vectors for each color are measured, and then the result is transferred to the CPU to recognize the vehicle color. The output colors are categorized into seven colors that include three achromatic colors: black, silver, and white and four chromatic colors: red, yellow, blue, and green. We construct feature vectors by using the histograms which consist of hue-saturation pairs and hue-intensity pairs. The weight factor is given to the saturation values. Our algorithm shows 94.67% of successful color recognition rate, by using a large number of sample images captured in various environments, by generating feature vectors that distinguish different colors, and by utilizing an appropriate likelihood function. We also accelerate the speed of color recognition by utilizing the parallel computation functionality in the GPU. In the experiments, we constructed a reference texture from 7,168 sample images, where 1,024 images were used for each color. The average time for generating a feature vector is 0.509ms for the $150{\times}113$ resolution image. After the feature vector is constructed, the execution time for GPU-based color recognition is 2.316ms in average, and this is 5.47 times faster than the case when the algorithm is executed in the CPU. Our experiments were limited to the vehicle images only, but our algorithm can be extended to the input images of the general objects.

External Context-Based Selective Resource Utilization Control Technique for Reducing Boot Time of Linux-Based Robot System (리눅스 기반 로봇 시스템의 부트 시간 단축을 위한 외부 컨텍스트 기반 선별적 자원 사용률 조정 기법)

  • Lee, Eunseong;Kim, Jungho;Yang, Beomjoon;Hong, Seongsoo
    • Proceedings of the Korean Society of Computer Information Conference
    • /
    • 2017.01a
    • /
    • pp.147-150
    • /
    • 2017
  • 지능형 로봇의 사용자 품질을 결정하는 주요 요소들 중 하나는 짧은 부트 시간이다. 로봇 시스템에서는 부팅 과정 중에 침입자인지, 자택 순찰, 개인 비서, 엔터테인먼트와 같은 다수의 응용들이 동시에 초기화되는데, 고품질의 사용자 경험을 제공하기 위해서는 사용자 응답성이 중요한 응용들이 우선적으로 초기화되어야한다. 이를 위해 리눅스 기반 로봇 시스템에서 부트 시간을 단축하기 위한 다양한 연구들이 진행되어 왔다. 하지만 이들은 단일 응용 각각에 대한 초기화 시간을 단축하는 연구들이며, 응용들 간에 CPU, 메모리, I/O와 같은 자원 경쟁에 의한 지연 요소를 고려하지 않고 있다. 본 논문에서는 응용들 간의 각종 자원경쟁들을 고려하여 사용자 응답성이 중요한 응용을 우선적으로 초기화하기 위한 외부 컨텍스트 기반 선별적 자원 사용률 조정기법을 제안한다. 이를 리눅스 기반 시스템 상에 구현하여 검증한 결과 응용의 부트 시간이 기존 대비 33.02% 단축됨을 확인했다.

  • PDF

Improvement in Reconstruction Time Using Multi-Core Processor on Computed Tomography (다중코어 프로세서를 이용한 전산화단층촬영의 재구성 시간 개선)

  • Chon, Kwon Su
    • Journal of the Korean Society of Radiology
    • /
    • v.9 no.7
    • /
    • pp.487-493
    • /
    • 2015
  • The reconstruction on the computed tomography requires much time for calculation. The calculation time rapidly increases with enlarging matrix size for improving image quality. Multi-core processor, multi-core CPU, has widely used nowadays and has provided the reduction of the calculation time through multi-threads. In this study, the calculation time of the reconstruction process would improved using multi-threads based on the multi-core processor. The Pthread and the OpenMP used for multi-threads were used in convolution and back projection steps that required much time in the reconstruction. The Pthread and the OpenMP showed similar results in the speedup and the efficiency.

The power management technique in the Embedded System (임베디드 시스템의 소모 전력 관리 기법)

  • Kim, Wha-Young;Kim, Young-Kil
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
    • /
    • 2008.05a
    • /
    • pp.159-164
    • /
    • 2008
  • The efficiently power management Is an important requirement traditionally in the mobile communication system which uses battery as their power source. Especially, it has been emphasized in the most recent devices, which has to provide high performance and various functions with an extended operating time. In this article, the adaptive Power management technique for the core processor unit in embedded systems used widely for the mobile system thanks to its advantage on power consumption and physical site, is proposed.

  • PDF

A real-time acoustic echo canceller implemented on the multimedia PC (멀티미디어 PC상에 구현된 실시간 음향 반향제거기)

  • Cha, Youn-Cheul;Yoo, Jae-Ha;Youn, Dae-Hee
    • Journal of the Korean Institute of Telematics and Electronics S
    • /
    • v.35S no.11
    • /
    • pp.184-193
    • /
    • 1998
  • In this paper, a real-time acoustic echo canceller is implemented using only PC's CPU without extra help from a DSP chip. The adaptive digital filter is designed efficiently so that it can be implemented in real-time and has a proper cancellation performance. It is proposed that a new double talk detector consumes a small computational complexity and guarantees the fast detection and robust operation. The real-time acoustic echo canceller consists of the full-duplex sound card and 166 MHz Pentium PC, and requires less than 10% CPU time.

  • PDF

A Method for accelerating training of Convolutional Neural Network (합성곱 신경망의 학습 가속화를 위한 방법)

  • Choi, Se Jin;Jung, Jun Mo
    • The Journal of the Convergence on Culture Technology
    • /
    • v.3 no.4
    • /
    • pp.171-175
    • /
    • 2017
  • Recently, Training of the convolutional neural network (CNN) entails many iterative computations. Therefore, a method of accelerating the training speed through parallel processing using the hardware specifications of GPGPU is actively researched. In this paper, the operations of the feature extraction unit and the classification unit are divided into blocks and threads of GPGPU and processed in parallel. Convolution and Pooling operations of the feature extraction unit are processed in parallel at once without sequentially processing. As a result, proposed method improved the training time about 314%.

A Parallel HDFS and MapReduce Functions for Emotion Analysis (감성분석을 위한 병렬적 HDFS와 맵리듀스 함수)

  • Back, BongHyun;Ryoo, Yun-Kyoo
    • Journal of the Korea society of information convergence
    • /
    • v.7 no.2
    • /
    • pp.49-57
    • /
    • 2014
  • Recently, opinion mining is introduced to extract useful information from SNS data and to evaluate the true intention of users. Opinion mining are required several efficient techniques to collect and analyze a large amount of SNS data and extract meaningful data from them. Therefore in this paper, we propose a parallel HDFS(Hadoop Distributed File System) and emotion functions based on Mapreduce to extract some emotional information of users from various unstructured big data on social networks. The experiment results have verified that the proposed system and functions perform faster than O(n) for data gathering time and loading time, and maintain stable load balancing for memory and CPU resources.

  • PDF

Embedded One Chip Computer Design for Hardware Implementation of Genetic Algorithm (유전자 알고리즘 하드웨어 구현을 위한 전용 원칩 컴퓨터의 설계)

  • 박세현;이언학
    • Journal of Korea Multimedia Society
    • /
    • v.4 no.1
    • /
    • pp.82-90
    • /
    • 2001
  • Genetic Algorithm(GA) has known as a method of solving NP problem in various applications. Since a major drawback of the GA is that it needs a long computation time, the hardware implementation of Genetic Algorithm is focused on in recent studies. This paper proposes a new type of embedded one chip computer fort Hardware Implementation of Genetic Algorithm. The proposed embedded one chip computer consists of 16 Bit CPU care and hardware of genetic algorithm. In contrast to conventional hardware oriented GA which is dependent on main computer in the process of GA, the proposed embedded one chip computer is independent on main computer. Conventional hardware GA uses the fixed length of chromosome but the proposed embedded one chip computer uses the variable length of chromosome by employing the efficient 16 bit Pipeline Unit. Experimental results show that the proposed one chip computer is applicable to the design of evolvable hardware for Random NRZ bit synchronization circuit.

  • PDF

A Java-based Performance Monitor for Networked Computer (네트워크 컴퓨터를 위한 자바 기반의 성능감시기)

  • Kim, Bong-Jun;Kim, Dong-Ho;Hwang, Seog-Chan;Kim, Myung-Ho;Choi, Jae-Young
    • Journal of KIISE:Computer Systems and Theory
    • /
    • v.27 no.2
    • /
    • pp.160-168
    • /
    • 2000
  • In this paper, we present a performance monitor to trace and evaluate the performance of programs running on networked computers. The performance monitor of the JaNeC is online/batch as well as event/time driven. Since it is implemented with the Java programming language, it provides us with high portability among heterogeneous computer systems, and friendly graphical user interface. This performance monitor consists of various views such as 'Task/Event Filter' and 'TimeLine', 'Task View', 'Task Hoistory', 'Message Passing View', 'Host Cpu View', which allow the user to easily analyze event and time during the program execution.

  • PDF

Parallel Computation of FDTD algorithm using CUDA (CUDA를 이용한 FDTD 알고리즘의 병렬처리)

  • Lee, Ho-Young;Park, Jong-Hyun;Kim, Jun-Seong
    • Journal of the Institute of Electronics Engineers of Korea CI
    • /
    • v.47 no.4
    • /
    • pp.82-87
    • /
    • 2010
  • Modern GPUs(Graphic Processing Units) provide computing capability higher than that of the general CPUs(Central Processor Units). With supports of programmability of graphics pipeline GP-GPU(General Purpose computation on GPU) has gained much attention expanding its application area. This paper compares sequential and massively parallel implementations of FDTD(Finite Difference Time Domain) algorithm using CUDA(Compute Unified Device Architecture). Experimental results show upto 45X speedup over conventional CPU execution.