• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.37-40
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• 2001

JBIG2 표준은 그레이 문서를 고압축의 이진 영상으로 부호화 하기위하여 선 영역(region of line-art), 하프톤 영역(region of Halftone), 텍스트 영역(region of Text)으로 세그먼트하여 각각 영역에 최적화 모드를 사용하여 부호화한다. 본 논문에서는 JBIG2에서 제공하는 세가지 모드의 코딩, 즉, 제네릭 영역(region of Generic) 코딩, 텍스트 영역을 위한 패턴 매칭(Pattern Matching) 코딩, 하프톤 영역을 위한 하프톤 코딩을 모두 구현하였다. 그리고, 각 영역을 세그먼트하는 방법을 개선하여 적용하여 세그먼트의 성능 향상을 이루었다. 특히, 부호화량이 많은 하프톤 영역의 세그먼트를 향상시켜 최적화 모드로 부호화 하도록 구현하였다. 팩스 테스트 영상(IEEE-l67a)으로 구현한 JBIC2 CODEC을 실험한 결과, 각 영역에 대한 세그먼트가 [6]의 방법에 의한 세그먼트보다 더 효율적으로 이루어졌으며 주관적 화질 또한 우수하였다.

• Proceedings of the Acoustical Society of Korea Conference
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• 1998.06c
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• pp.151-154
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• 1998

이중 전송율(5.3 과 6.3kbit/s)을 제공하는 G.723.1 음성 코더는 공중망을 통한 H.324 POTS 영상 회의 규격의 음성 코더로 채택된 것으로, MPMLQ, ACELP 알고리즘에 근거한다. 본 논문에서는 Annex A를 포함한 G.723.1 음성 코더 알고리즘을 C&S Technology에서 개발한 음성 신호 처리를 위한 범용 DSP인 CSD17C00 칩을 이용하여 실시간 응용이 가능하도록 구현하였다. G.723.1 에 대한 양방향 평가가 Codec loopback을 통해 수행되었으며, ITU에서 제공한 테스트 절차에 따라 평가되었다. 또한, 본 논문에서 구현된 G.723.1 음성 코더는 27MIPS의 계산 속도를 갖으며, 프로그램 ROM의 크기는 8.85K Words이고, 10K 데이터 ROM과 4K 데이터 RAM을 필요로 하고 있다. 경쟁 제품과의 MOS 측정 음질 평가를 실시한 결과, CSD17C00에서의 음질 성능이 더 우수함을 입증 함으로써, 본 논문에서 보여준 CSD17C00을 기반으로 구현된 G.723.1 알고리즘의 실시간 구현기술의 타당성을 검증하게 되었다.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1288-1291
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• 2002

In this paper, we present a design of mpeg-4 video codec chip to reduce the power consumption using frame level clock gating and motion estimation skip scheme. It performs 30 grames/s of codec (encoding and decoding) mode with quarter-common intermediate format(QCIF) at 27MHz. A novel low-power techniques were implemented in architectural level, which is 35% of the power dissipation for a conventional CMOS design. This chip performs MPEG-4 Simple Profile Level 2(Simple@L2) and H.263 base mode. Its contains 388,885 gates, 662k bits memory, and the chip size was 9.7 mm x 9.7 mm which was fabricated using 0.35 micron 3-layers metal CMOS technology.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.155-164
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• 1996

The architecture of a programmable video codec IC is described that employs multiple vector processors in a single chip. The vector processors operate in parallel and communicate with one another through on-chip shared memories. A single scalar control processor schedules each vector processor independently to achieve real-tiem video coding with special vector instructions. With programmable interconnection buses, the proposed architecture performs multi-processing of tasks and data in video coding. Therefore, it can provide good parallelism as well as good programmability. especially, it can operate multithread video coding, which processes several independent image sequences simultaneously. We explain its scheduling, multithred video coding, and vector processor architectures. We implemented a prototype video codec with a 0.8um CMOS cell-based technology for the multi-standard videophone. This codec can execute video encoding and decoding simultaneously for the QCIF image at a frame rate of 30Hz.

• Speech Sciences
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• v.11 no.2
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• pp.227-235
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• 2004

In this paper, we proposed a new practical implementation method of the lattice transversal joint (LTJ) adaptive filter using speech codec's information. And it was applied to the adaptive echo cancellation problem to verify the efficiency of the proposed method. Realtime implementation of the LTJ adaptive filter is very difficult due to high computational complexity for the filter coefficients compensation. However, in case of using speech codec, complexity can be reduced since linear predictive coding (LPC) coefficients are updated each frame or sub-frame instead of every sample. Furthermore, LPC coefficients can be acquired from speech decoder and transformed to the reflection coefficients. Therefore, the computational complexity for updates of the reflection coefficients can be reduced. The effectiveness of the proposed LTJ adaptive filter was verified by the experiments about convergence and tracking performance of the adaptive echo canceller.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1984.04a
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• pp.9-12
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• 1984

A digital TV CODEC has been implemented. This CODEC uses a pulse code modulation with a resolution of 9 bits per sample and generates digital ouput at the rate of 90.194Mb/s. In this system, we aadopted a horizontal blanking control scheme to meet the contraint of 90.194Mb/s transmission rete, conswequently ontaining data compression of 9.4%, our system's performances have been measured. Its SNR

• ETRI Journal
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• v.27 no.6
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• pp.818-821
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• 2005

Recently, MPEG has opened activity to standardize scene representation for lightweight applications such as in mobile phones. The standard is named lightweight applications scene representation (LASeR) and can be applied to improve and make efficient rich media applications and services on mobile devices. In this standard, we proposed an efficient type codec for point data to maximize the bit efficiency of LASeR. In this paper, we describe the new method and the test results of the proposed scheme.

• Proceedings of the IEEK Conference
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• 2002.06d
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• pp.167-170
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• 2002

In this paper, we implement a 2.4 kbps STC speech codec using the TMS320C6201 DSP The main job for this work is twofold: one is to convert floating-point operation in the codec into fixed-point operation while maintaining the high resolution, and the other is to optimize the program to make it run in real time with memory size as small as possible. The implemented decoder uses 54.8 kbyte of program memory, 29.7 kbyte of data ROM and 55.2 kbyte of data RAM, respectively. It also uses about 45% of maximum computation capacity of TMS320C6201.

• Proceedings of the KIEE Conference
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• 1998.07g
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• pp.2480-2482
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• 1998

In this paper, the implementation of dual rate ADPCM using G.723 16Kbps and 40Kbps speech codec algorithm is handled. For small signals, the low rate 16Kbps coding algorithm shows the same SNR as the high rate 40Kbps coding algorithm, while the low rate 16Kbps coding algorithm shows the lower SNR than the high rate 40Kbps coding algorithm for large signal. To obtain the good trade-off between the data rate and synthesized speech quality, we applied low rate 16Kbps for the small signal and high rate 40Kbps for the large signal. Various threshold values determining the rate are tested for good trade off data rate and speech quality. Also the low pass filter effect of speech input and output devices is simulated at several cut-off frequencies. To simulation result shows the good speech quality at a low rate comparing with 16Kbps & 40Kbps.

• ETRI Journal
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• v.33 no.2
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• pp.145-154
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• 2011

We present a novel video codec for supporting entertainment-quality video. It has new coding tools such as an intra prediction with offset, integer sine transform, and enhanced block-based adaptive loop filter. These tools are used adaptively in the processing of intra prediction, transform, and loop filtering. In our experiments, the proposed codec achieved an average reduction of 13.35% in BD-rate relative to H.264/AVC for 720p sequences.