• 한국세라믹학회:학술대회논문집
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• 한국세라믹학회 2003년도 춘계총회 및 연구발표회 초록집
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• pp.78.2-78
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• 2003

• 한국세라믹학회:학술대회논문집
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• 한국세라믹학회 2003년도 춘계총회 및 연구발표회 초록집
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• pp.29.2-29
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• 2003

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2008년도 춘계학술대회 논문집
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• pp.361-362
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• 2008

• 한국재료학회:학술대회논문집
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• 한국재료학회 1998년도 IUMRS-ICEM ABSTRACT BOOK
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• pp.106.1-106
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• 1998

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.485-485
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• 2009

Double side polishing process has been used for various industrial applications, such as polishing of semiconductor substrates and flat panel display glasses. In wafer manufacturing, double side polishing process is applied to improve wafer flatness and to minimize particle generation from wafers in device manufacturing processes, which is recognized as one of the most important processes. Whereas the kinematical modeling and analysis results of single side polishing, extensively used for chemical-mechanical polishing (CMP) in device manufacturing, are well investigated, the studies in conjunction with double side polishing are barely carried out, due to the complication of polishing system and the uncertainty of wafer motion in the carrier. This paper suggests the derivation of kinematical model with consideration of carrier and wafer motion in double side polishing, and then presents the effect of kinematical parameters on material removal amount and its non-uniformity. The kinematical analysis results help to understand the double side polishing process and to control the polishing results.

• 마이크로전자및패키징학회지
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• 제20권4호
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• pp.81-85
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• 2013

웨이퍼 적층 기술은 반도체 전 후 공정을 이용한 효과적인 방법으로 향후 3D 적층 시스템의 주도적인 발전방향이라고 할 수 있다. 웨이퍼 레벨 3D 적층 시스템을 제조하기 위해서는 TSV (Through Si Via), 웨이퍼 본딩, 그리고 웨이퍼 thinning의 단위공정 개발 및 웨이퍼 warpage, 열적 기계적 신뢰성, 전력전달, 등 시스템적인 요소에 대한 연구개발이 동시에 진행되어야 한다. 본 연구에서는 웨이퍼 본딩에 가장 중요한 역할을 하는 Cu CMP (chemical mechanical polishing) 공정에 대한 특성 분석을 진행하였다. 8인치 Si 웨이퍼에 다마신 공정으로 Cu 범프 웨이퍼를 제작하였고, Cu CMP 공정과 oxide CMP 공정을 이용하여 본딩 층 평탄화에 미치는 영향을 살펴보았다. CMP 공정 후 Cu dishing은 약 $180{\AA}$이었고, 웨이퍼 표면부터 Cu 범프 표면까지의 최종 높이는 약 $2000{\AA}$이었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 춘계학술대회 논문집 전자세라믹스 센서 및 박막재료 반도체재료 일렉트렛트 및 응용기술
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• pp.35-38
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• 2000

In this study, the rise throughput and the stability in fabrication of device can be obtained by applying of CMP process to STI structure in 0.l8um semiconductor device. Through reverse moat pattern process, reduced moat density at high moat density, STI CMP process with low selectivity could be to fit polish uniformity between low moat density and high moat density. Because this reason, in-situ motor current end point detection method is not fit to the current EPD technology with the reverse moat pattern. But we use HSS without reverse moat pattern on STI CMP and take end point current sensing signal.[1] To analyze sensing signal and test extracted signal, we can to adjust wafer difference within $110{\AA}$.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
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• pp.107-108
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• 2005

In this paper, we first applied the chemical mechanical polishing (CMP) process to the planarization of ferroelectric film in order to obtain a good planarity of electrode/ferroelectric film interface. $Pb_{1.1}(Zr_{0.52}Ti_{0.48})O_3$ (shortly PZT) ferroelectric film was fabricated by the sol-gel method. And then, we compared the structural characteristics before and after CMP process of PZT films. Their dependence on slurry composition was also investigated. We expect that our results will be useful promise of global planarization for ferroelectric random access memories (FRAM) application in the near future.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 영호남 합동 학술대회 및 춘계학술대회 논문집 센서 박막 기술교육
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• pp.103-104
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• 2006

In this paper. we first applied the chemical mechanical polishing (CMP) process to the planarization of ferroelectric film in order to obtain a good planarity of electrode/ferroelectric film interlace. $Pb_{1.1}(Zr_{0.52}Ti_{0.48})O_3$ (shortly PZT) ferroelectric film was fabricated by the sol-gel method. And then. we compared the structural characteristics before and alter CMP process of PZT films. Their dependence on slurry composition was also investigated. We expect that our results will be useful promise of global planarization for ferroelectric random access memories (FRAM) application in the near future.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 추계학술대회 논문집 전기물성,응용부문
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• pp.83-84
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• 2006

Chemical mechanical polishing (CMP) process has been attracted as an essential technology of multi-level interconnection. However, the COO (cost of ownership) is very high, because of high consumable cost. Especially, among the consumables, slurry dominates more than 40 %. So, we focused how to reduce the consumption of raw slurry. In this paper, $MnO_2$ abrasives were added de-ionized water (DIW) and pH control as a function of KOH contents. Also, the addition effects of $MnO_2$ abrasives and the diluted silica slurry (DSS) on CMP performances were evaluated. Finally, we have investigated the possibility of new abrasive for the oxide CMP application.