• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2011년도 추계학술대회
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• pp.448-451
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• 2011

SoC에서 칩 내부의 온도를 측정하기 위한 proportional-to-absolute-temperature (PTAT) 회로와 sensing 된 아날로그 신호를 디지털로 변환하기 위해 4-bit analog-to-digital converter (ADC)로 구성된 temperature sensor를 제안한다. CMOS 공정에서 vertical PNP 구조를 이용하여 PTAT 회로가 설계되었다. 온도변화에 둔감한 ADC를 구현하기 위해 아날로그 회로를 최소로 사용하는 successive approximation (SA) ADC가 이용되었다. 4-bit SA ADC는 capacitor DAC와 time-domain 비교기를 이용함으로 전력소모를 최소화하였다. 제안된 temperature sensor는 2.5V $0.25{\mu}m$ 1-poly 9-metal CMOS 공정을 이용하여 설계되었고, $50{\sim}150^{\circ}C$ 온도 범위에서 동작한다. Temperature sensor의 면적과 전력 소모는 각각 $130{\times}390\;um^2$과 868 uW이다.

• 한국정보통신학회논문지
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• 제13권6호
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• pp.1117-1122
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• 2009

본 논문에서는 온도 센서 및 온도 측정을 위한 제어회로를 설계하였다. 설계된 회로는 기존의 방법들과는 달리 일반적인 CMOS(Complementary Metal Oxide Semiconductor) 공정에서 추가 공정없이 제작 가능하도록 설계하였으며, 온도는 디지털 값으로 출력 되도록 구성하였다. 설계되어진 회로는 5volts 공급전압을 사용하였으며, 0.5${\mu}m$ CMOS 공정을 사용하였다. 온도 측정을 위한 회로는 PWM(Pulse Width Modulation) 제어회로, VCO(Voltage controlled oscillator), 카운터 그리고 레지스터로 구성되어 있다. PWM 제어회로의 동작 주파수는 23kHz 이며, VCO의 동작 주파수는 416kHz, 1MHz, 2MHz를 사용하였다. 회로의 동작은 SPICE(Simulation Program with Integrated Circuit Emphasis)를 사용하여 확인 하였다.

• 한국정보통신학회논문지
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• 제11권3호
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• pp.555-562
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• 2007

CMOS 이미지 센서로부터 수신한 베이어 입력 스트림을 디스플레이 장치로 보기위해서는 영상 신호처리를 수행해야 한다. 즉, 이러한 영상 신호처리를 수행한 부분을 ISP(Image Signal Processor)라 한다. ISP 처리를 통해서 실제 원본 이미지를 볼 수 있다. ISP는 감마교정, 인터폴레이션, 공간적 변환, 이미지 효과, 이미지 스케일, AWB, AE, AF 등과 같은 기능을 수행한다. 본 논문에서는 CMOS 카메라 이미지 센서용 ISP를 모델링하여 최적화 알고리즘을 소프트웨어 검증을 통해 도출하였으며, VHDL 언어를 이용하여 설계하고 ModelSim6.0a 시뮬레이터를 이용하여 검증하였다. 또한 보드 레벨의 검증을 위해 PCI 인터페이스를 이용하여 설계한 ISP 모듈을 자일링스 XCV-1000e에 다운로드하여 결과를 확인하였다.

• 센서학회지
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• 제26권2호
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• pp.85-90
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• 2017

A wide dynamic range (WDR) CMOS image sensor (CIS) was developed with a specialized readout architecture for realizing high-sensitivity (HS) and low-sensitivity (LS) reading modes. The proposed pixel is basically a three-transistor (3T) active pixel sensor (APS) structure with an additional transistor. In the developed WDR CIS, only one mode between the HS mode for relatively weak light intensity and the LS mode for the strong light intensity is activated by an external controlling signal, and then the selected signal is read through each column-parallel readout circuit. The LS mode is implemented with the column capacitors and a feedback structure for adjusting column capacitor size. In particular, the feedback circuit makes it possible to change the column node capacitance automatically by using the incident light intensity. As a result, the proposed CIS achieved a wide dynamic range of 94 dB by synthesizing output signals from both modes. The prototype CIS is implemented with $0.18-{\mu}m$ 1-poly 6-metal (1P6M) standard CMOS technology, and the number of effective pixels is 176 (H) ${\times}$ 144 (V).

• 센서학회지
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• 제15권5호
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• pp.341-346
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• 2006

We have fabricated SOI CMOS active pixel image sensor with the pinned photodiode on handle wafer in order to reduce dark currents and improve spectral response. The structure of the active pixel image sensor is 4 transistors APS which consists of a reset and source follower transistor on seed wafer, and is comprised of the photodiode, transfer gate, and floating diffusion on handle wafer. The source of dark current caused by the interface traps located on the surface of a photodiode is able to be eliminated, as we apply the pinned photodiode. The source of dark currents between shallow trench isolation and the depletion region of a photodiode can be also eliminated by the planner process of the hybrid bulk/SOI structure. The photodiode could be optimized for better spectral response because the process of a photodiode on handle wafer is independent of that of transistors on seed wafer. The dark current was about 6 pA at 3.3 V of floating diffusion voltage in the case of transfer gate TX = 0 V and TX=3.3 V, respectively. The spectral response of the pinned photodiode was observed flat in the wavelength range from green to red.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2008년도 추계종합학술대회 B
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• pp.571-574
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• 2008

본 논문에서는 개선된 회로를 적용한 $256{\times}256$ 픽셀 저항형 지문센서를 제안하고 있다. 단위 픽셀 수준의 센싱 회로는 가변적인 전류를 전압으로 변환하여 이진 디지털 신호로 만든다. 정전기에 효과적으로 대처할 수 있는 인접 픽셀 간 전기적 차폐 레이아웃 구조를 제안하고 있다. 전체회로는 단위 센서 회로를 확장하여 ASIC 설계방식을 통하여 설계한 뒤 로직 및 회로에 대하여 모의실험을 하였다. 전체회로는 $0.35{\mu}m$ 표준 CMOS 공정규칙을 적용하여 센서블록은 전주문 방식을 적용하고 전체 칩은 자동배선 틀을 이용하여 반주문 방식으로 레이아웃을 실시하였다.

• 센서학회지
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• 제26권4호
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• pp.223-227
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• 2017

Conventional CMOS image sensors (CISs) have a trade-off relationship between dynamic range and sensitivity. In addition, their sensitivity is determined by the photodiode capacitance. In this paper, CISs that consist of dual-sensitivity photodiodes in a unit pixel are proposed for achieving wide dynamic ranges. In the proposed CIS, signal charges are generated in the dual photodiodes during integration, and these generated signal charges are accumulated in the floating-diffusion node. The signal charges generated in the high-sensitivity photodiodes are transferred to the input of the comparator through an additional source follower, and the signal voltages converted by the source follower are compared with a reference voltage in the comparator. The output voltage of the comparator determines which photodiode is selected. Therefore, the proposed CIS composed of dual-sensitivity photodiodes extends the dynamic range according to the intensity of light. A $94{\times}150$ pixel array image sensor was designed using a conventional $0.18{\mu}m$ CMOS process and its performance was simulated.

• 센서학회지
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• 제24권2호
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• pp.79-82
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• 2015

This paper proposes a novel complementary metal oxide semiconductor (CMOS) active pixel sensor (APS) and presents its performance characteristics. The proposed APS exhibits a linear-logarithmic response, which is simulated using a standard $0.35-{\mu}m$ CMOS process. To maintain high sensitivity and improve the dynamic range (DR) of the proposed APS at low and high-intensity light, respectively, two additional nMOSFETs are integrated into the structure of the proposed APS, along with a photogate. The applied photogate voltage reduces the sensitivity of the proposed APS in the linear response regime. Thus, the conversion gain of the proposed APS changes from high to low owing to the addition of the capacitance of the photogate to that of the sensing node. Under high-intensity light, the integrated MOSFETs serve as voltage-light dependent active loads and are responsible for logarithmic compression. The DR of the proposed APS can be improved on the basis of the logarithmic response. Furthermore, the reference voltages enable the tuning of the sensitivity of the photodetector, as well as the DR of the APS.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.341-344
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• 2002

This paper is proposed a 8-bit analog to digital converter for CMOS image sensor. A analog to digital converter for CMOS image sensor is required function to control gain. Frequency divider is used In control gain in this proposed analog to digital converter. At 3.3 Volt power supply, total static power dissipation is 8㎽ and programmable gain control range is 30㏈. Newly suggested analog to digital converter is designed by 0.35um 2-poly 4-metal CMOS technology.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.224-227
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• 1999

This paper presents a design of the real-time preprocessor for CMOS image sensor suitable to the digital camera applications. CMOS image sensor offers some advantages in on-chip integration, system power reduction, and low cost. However, it has a lower-quality image than CCDs. We describe an image enhancement algorithm, which includes color interpolation, color correction, gamma correction, sharpening, and automatic exposure control, to compensate for this disadvantage, and present its efficient hardware architecture to implement on the real-time processor. The presented real-time preprocessor was designed using VHDL, and it contains about 19.2K logic gates. We also implement our system on FPGA chips in order to provide the real-time adjustment and it was successfully tested.