• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.321-327
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• 2006

This paper presents low power and high frequency design of instructions using ad-hoc techniques at transistor level for full custom and semi-custom ASIC(Application Specific Integrated Circuit) designs. The proposed design has been verified at high level using Verilog-HDL and simulated using ModelSim for the logical correctness. It is then observed at the layout level using LASI using $0.25{\mu}m$ technology and analyzed for timing characteristic under Win-spice simulation environment. The result shows the significant reduction up to $35\%$ in the power consumption by any general purpose processor like RISC or CISC. A significant reduction in the propagation delay is also observed. increasing the frequency for the fetch and execute cycle for the CPU, thus increasing the overall frequency of operation.

• Proceedings of the Korean Information Science Society Conference
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• 2000.04a
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• pp.466-468
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• 2000

ARM 프로세서는 CISC 보다는 간단하게 디자인된 RISC로서 내장 응용프로그램에 적합하기 때문에 앞으로 모든 디지털 기기에 ARM 코어를 기반으로 한 핵심 칩들이 생산된다. 그러나 명령어가 CISC보다는 적기 때문에 주어진 작업에 대해 완전한 처리를 위해서는 보다 많은 명령어들을 필요로 한다. 이러한 ARM 프로세서에서 데이터를 전송할 때 사용하는 메모리 영역과 레지스터들을 프로그램과 함께 분석하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.4
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• pp.85-94
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• 2003

The asynchronous design methods proved to have the higher performance in power consumption and execution speed than synchronous ones because it just needs to activate the required module without feeding clock in the system. Despite the advantage of CISC machine providing the variable addressing modes and instructions, its execution scheme is hardly suited for a synchronous Pipeline architecture and incurs a lot of overhead. This paper proposes a novel asynchronous pipeline architecture, A80sl, whose instruction set is fully compatible with that of Intel 80C51, an embedded micro controller. We classify the instructions into the group keeping the same execution scheme for the asynchronous pipeline and optimize it eliminating the bubble stage that comes from the overhead of the multi-cycle execution. The new methodologies for branch and various instruction lengths are suggested to minimize the number of states required for instructions execution and to increase its parallelism. The proposed A80C51 architecture is synthesized with 0.35${\mu}{\textrm}{m}$ CMOS standard cell library. The simulation results show higher speed than that of Intel 80C51 with 36 MHz and other asynchronous counterparts by 24 times.

• 전기의세계
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• v.46 no.9
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• pp.5-8
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• 1997

본 글에서는 CISC, RISC, 수퍼스칼라. VLIW를 소개하고 각각의 프로세서가 출현하게 된 배경과 특징, 장단점 등을 다룬다.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 2006.06a
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• pp.79-82
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• 2006

다중 사용자 환경에서 안전한 대리서명을 설계하는 연구의 하나로, threshold 서명 방식을 대리서명에 적용한 threshold 대리서명 기법들이 최근 많이 제안되고 있다. Xue와 Cao가 2004년 발표한 threshold 대리서명 기법은 Hsu-Wu 자체인증 공개키 방식 (Self-certified public key)을 기반으로 설계된 것으로 WISA 2005, CISC 2005, ICCSA 2006에서 각각 다른 취약성이 밝혀진 바 있다. 특히 CISC 2005, ICCSA 2006에서는 각각의 공격방법에 내성을 가질 수 있도록 Xue-Cao 기법을 개선하는 방안을 같이 제시하였다. 본 논문에서는 이러한 개선안이 적용된 Xue-Cao 기법에 대해 두 가지 종류의 원서명자 위조 공격이 가능함을 보인다. 하나는 Hsu-Wu 자체인증 공개키 방식의 취약성을 이용하는 것이고 다른 하나는 Xue-Cao 기법의 서명 생성 방식의 취약성에 기반한 것이다. 이러한 공격을 통해 개선된 Xue-Cao 기법 또한 대리자 보호, 부인방지와 같은 안전성 조건을 만족하지 않음을 확인한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.6
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• pp.71-80
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• 2004

In this paper, we study for the design and verification of a 16 bits micro controller, which is compatible with a 8 bits micro controller, 8051, widely used in the industrial fields these days. To confirm our design, we verified our design for all instruction sets and various combinational sets of them. Also we propose a new idea for the verification of various instruction sets, We verified our design through some application programs such as IMA-ADPCM, SOLA. Finally, we verified our design for all instruction sets and application programs through an application board, used Xilinx FPGA(XCVl000-560C). After the comparison our design with a 8051 for various cases, We concluded that we could substitute our design for a 8051 and our design could be operated more powerfully than a 8051.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 1998.12a
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• pp.345-353
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• 1998

본 논문에서는 next-bit 검정의 이론적 배경을 고찰하고, 실제적인 검정법으로 구현된 검정방법에 대하여 조사 분석한다. Next-bit 검정 이론은 Schrift와 Shamir가 제시한 다양한 검정방법을 중심으로 소개한다. 그리고 구현된 통계적 검정 방법은 ACISP'96에서 발표된 검정법과 CISC'97에서 제안된 검정법을 비교 분석한다.

• Korean Journal of Mathematics
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• v.28 no.1
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• pp.149-157
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• 2020

Some basic properties in connection with generalized relative order and generalized relative lower order of analytic functions in the unit disc have been dicussed in this article.

• The Transactions of the Korea Information Processing Society
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• v.7 no.2
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• pp.470-476
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• 2000

This paper describes an IP design of a low-power microcontroller using an architecture level design methodology instead of a transistor level. To reduce switching capacitance, the register-toregister data transfer is adopted to frequently used register transfer micro-operations. Also, distributed buffers are proposed to reduce a input data rising edge time. To reduce power consumption without any loss of performance, pipeline processing should be used. In this paper, a 4-stage pipelined datapath being able to process CISC instructions is designed. Designed microcontroller lessens power consumption by 20%. To measure a power consumption, the SYNOPSYS EPIC powermill is used.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.21 no.5
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• pp.27-33
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• 2011

At FDTC'05 and CISC-W'10, the authors showed that if they decrease the number of rounds of AES and Triple-DES by using the fault injections, it is possible to recover the secret key of the target algorithms, respectively. In this paper, we propose a key recovery attack on HMAC by using the main idea of these attacks. This attack is applicable to HMAC based on MD-family hash functions and can recover the secret key with the negligible computational complexity. Particularly, the attack result on HMAC-SHA-2 is the first known key recovery attack result on this algorithm.