• 한국군사과학기술학회지
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• 제13권3호
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• pp.405-412
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• 2010

The purpose of this paper is to compare complexity and to assess flexibility of competing transponder architectures for satellite communication services. For performance comparison, we consider three channelization techniques: digital down converter(DDC) based on the use of the cascaded integrator-comb(CIC) filter, tuneable pipeline frequency transform(T-PFT) based on the tree-structure(TS) and variable oversampled complex-modulated filter banks(OCM-FB) based on the polyphase FFT(P-FFT). The comparison begins by presenting a basic architecture of each channelization method and includes analytical expressions of the number of multiplications as a computational complexity perspective. The analytical results show that DDC with CIC filter requires the heavy computational burden and the perfect flexibility. T-PFT based on the TS provides the almost perfect flexibility with the low complexity over DDC with the CIC filter for a large number of sub-channels. OCM-FB based on the P-FFT shows the high flexibility and the best computational complexity performance compared with other approaches.

• 한국정보통신학회논문지
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• 제14권8호
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• pp.1776-1782
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• 2010

간섭형 Fiber optic gyroscope(FOG)는 Sagnac 효과를 이용한 회전센서로 알려져 있으며, 성능 개선을 위한 연구가 수행되어 왔다. 본 논문은 개루프 방식의 FOG 개발과 FPGA를 이용한 디지털 신호처리 기술을 다루고 있다. 첫 번째 목표는 양호한 bias stability(0.22deg/h), Scale factor stability, 단일모드 광섬유를 이용한 낮은 Angle randomwalk(0.07deg/$\sqrt[]{h}$)와 저가의 중급 자이로(Pointing grade)의 설계를 목표로 하고 있다. 두 번째 목표는 광검출기의 출력신호를 고속 ADC로 직접 변환 후 디지털 신호처리를 하는 FOG용 FPGA 개발이다. 본 연구에서 사용한 Cascaded integrator-comb(CIC)타입의 데시메이션 필터는 Adder와 Shift register만으로 구성되어 적은 계산량을 요구하므로 모든 디지털 FOG 프로세서를 저가의 프로세서로도 사용이 가능하다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년 학술대회 논문집 정보 및 제어부문
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• pp.388-390
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• 2006

This paper presents a hybrid SoC design for phase detection of single tone signal. The designed hybrid SoC is composed of three functional blocks, i.e., an analog to digital converter module, a phase detection module and a controller module. A design of the controller module is based on a 16-bit RISC architecture. An I/O interface and an LCD control interface for transmission and display of phase measurement values are included in the design of the controller module. A design of the phase detector is based on a recursive sliding-DFT. The recursive architecture effectively reduces the gate numbers required in the implementation of the module. The ADC module includes a single-bit second-order sigma-delta modulator and a digital decimation filter. The decimation filter is designed to give 98dB of SNR for the ADC. The effective resolution of the ADC is enhanced to 98dB of SNR by the incorporation of a pre FIR filter, a 2-stage cascaded integrator- comb(CIC) filter and a 30-tab FIR filter in the decimation. The hybrid SoC is verified in FPGA and implemented in 0.35 CMOS Technology.