• 제어로봇시스템학회논문지
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• 제14권4호
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• pp.327-331
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• 2008

An in-line wet etch/cleaning system was established for the research and development in wet etch process as a formation of electrode such as metal or transparent conductive oxide layer. A reverse moving system was equipped in the in-line wet etch/cleaning system for the alternating motion of glass substrate in a wet etch bath of the system. Therefore, it was possible for the glass substrate to be moved back and forth and it was possible to reduce the size of the system by using the reversing moving system. For the effect of the alternating motion of substrate on the etch rate in the in-line wet etch bath, indium tin oxide(ITO) patterns were obtained through wet etch process in the in-line system in which the substrate was moved back and forth. From the CD(critical dimension) skews resulted from the ADI CD and ACI CD of the ITO patterns, it was concluded that the alternating motion of glass substrate are possible to be applied to the mass production of wet etch process.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.863-866
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• 2008

For the cost reduction in the fabrication of display panels, a reverse moving system was equipped to a compacted in-line wet etch/cleaning system. For the effect of the alternating movement of substrate on the wet etch process, ITO layers were etched in various moving modes of substrates and the results were compared and analyzed.

• 대한전자공학회논문지SD
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• 제39권1호
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• pp.31-38
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• 2002

0.35㎛-비아(via) 식각공정을 개선하기 위하여 C₂F/sub 6/가스의 식각특성을 분석하였다. 실험한 재료는 TEOS/SOG/TEOS 막을 올린 8인치 웨이퍼이며, 실험의 기법은 직교행열(Orthogonal array matrix) 실험 방식을 활용하였다. 산화막 식각에 이용된 장비는 transformer coupled plasma(TCP) source 방식이며 고밀도 플라즈마(HDP)장비이다. 실험의 결과는, 실험변수의 범위 내에서 C₂F/sub 6/는 0.8㎛/min-1.l㎛/min 범위의 식각속도를 보이며 균일도(Uniformity)는 ±6.9%미만으로 측정되었다. CD 변화(skew)는 식각 전과 후를 비교하여 10% 미만이었고 그 결과 비등방성(anisotropic) 식각의 특성이 우수하였다. C₂F/sub 6/를.20sccm 공급할 때 문제점이 발견되지 않았지만 14sccm을 공급하면 SOG 막의 내벽이 침식당하는 문제점이 있었다. 결과적으로 C₂F/sub 6/는 HDP TCP에서 빠른 식각비와 넓은 공정창(process window)을 가진 식각특성을 나타내었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집 Vol.14 No.1
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• pp.181-184
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• 2001

Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STD structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters. we studied the correlation between CMP thickness of STI using high selectivity slurry. DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased. the N-poly foot is deteriorated. and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point,, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by $100\AA$. 3.2 $u\AA$ of IDSN is getting better in base 1 condition. In POE 50% condition. 1.7 $u\AA$ is improved. and 0.7 $u\AA$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집
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• pp.181-184
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• 2001

Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STI) structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters, we studied the correlation between CMP thickness of STI using high selectivity slurry, DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased, the N-poly foot is deteriorated, and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by 100 ${\AA}$, 3.2 u${\AA}$ of IDSN is getting better in base 1 condition. In POE 50% condition, 1.7 u${\AA}$ is improved, and 0.7 u${\AA}$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.