• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.1C
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• pp.12-18
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• 2008

This paper This paper proposes a new inverse-quantization(IQ) table interpolation algorithm, specialized Digital Signal Processor(DSP) instructions and hardware architecture for digital audio codecs. Non-linear inverse quantization algorithm is representatively used in both MPEG-1 Layer-3 and MPEG-2/4 Advanced Audio Coding(AAC). The proposed instructions are optimized for the non-linear inverse quantization. The proposed algorithm can minimize operational complexity which reduces total computational load. Performance comparisons show a significant improvement of average error. The proposed instructions and hardware architecture can reduce 20% of the instruction counts and minimize computational loads of IQ algorithms effectively compared with existing IQ table interpolation algorithms. Proposed algorithm can implement commercial DSPs.

• Journal of the military operations research society of Korea
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• v.26 no.2
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• pp.101-119
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• 2000

US DoD designated the High LEvel Architecture (HLA) as the standard technical architecture for all military simulation since 1996. HLA will supercede the current Distributed Interactive Simulation(DIS) and Aggregated LEvel Simulation Protocol(ALSP) methods by no funds for developing/modifying non-HLA compliant simulations. The new architecture specifies Rules which define relationships among federation components, an Objects Model Template which species the form which simulation elements are described, and an Interface Specification which describes the way simulations interact during operations. HLA is named as standard architecture in NATO, Australia and many other militaries. Also, it will be IEEE standard in the near future. It goes without saying that ROK military whose simulation models are almost from US must be prepared in areas such as ROK-US combined exercise, training, weapon system acquisition, interface models with C4I system, OPLAN analysis, operations, and os on. In this paper, we propose several effective alternatives and issues for ROK Defense Modeling and Simulation under the transition of new HLA architecture. Those include secure the kernel of new simulation technology and develop our own conceptual model, RTI software, prototype federation for each service and aggregated one. In order to challenge the new simulation architecture effectively, we should innovate our current defense modeling and simulation infrastructure such s manpower, organization, budget, research environment, relationships among academia and industry, and many others.

• Advances in environmental research
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• v.3 no.4
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• pp.367-377
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• 2014

In this study, we investigated a life cycle assessment (LCA) of six roof-waterproofing systems [asphalt (C1), synthetic polymer-based sheet (C2), improved asphalt (C3), liquid applied membrane (C4), Metal sheet with asphalt sheet (N1), and liquid applied membrane with asphalt sheet (N2)]for reinforced concrete building using an architectural model. To acquire accurate and realistic LCA results, minimum units of material compositions for life cycle inventory and real data for compositions of waterproofing materials were used. Considering only materials and energy demands for waterproofing systems per square meter, higher greenhouse gas (GHG) emissions could be generated in the order of C1 > N2 > C4 > N1 > C2 > C3 during construction phase. However, the order was changed to C1 > C4 > C3 > N2 > N1 > C2, when the actual architecture model was applied to the roof based on each specifications. When an entire life cycle including construction, maintenance, and deconstruction were considered, the amount of GHG emission was in the order of C4 > C1 > C3 > N2 > C2 > N1. Consequently, N1 was the most environmental-friendly waterproofing system producing the lowest GHG emission. GHG emissions from maintenance phase accounted for 71.4%~78.3% among whole life cycle.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.11c
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• pp.1987-1990
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• 2002

CBD를 지원하는 소프트웨어 개발기법이 최근 많은 관심과 함께 도입되면서 이를 효과적으로 운용할 수 있는 아키텍처기반의 조립 및 활용분야가 활발히 연구되고 있다. 특히, C2(Chiron-2) 스타일 아키텍처는 GUI를 지원하기 위한 메시지방식의 컴포넌트 조합기법이라는 점에서 많은 관심을 받고 있다. 그러나, 서버측 컴포넌트 모델인 EJB(Enterprise Java Beans)의 경우 쓰레드를 포함할 수 없으며, 직접적인 메소드를 호출하는 방식으로 이하여 GUI 기반 메시지 방식에서는 수정이 불가피하다. 따라서, 본 논문에서는 C2 스타일 아키텍처에 EJB 컴포넌트를 적용할 수 있는 기법을 제안하고자한다. 즉 디자인패턴 중 구조패턴의 하나인 Adapter패턴을 이용하여 EJB 컴포넌트를 C2 프레임워크에 적용할 수 있는 컴포넌트 쓰레드로 생성 및 운영하였다. 이를 위하여, J2EE 1.2.1과 J2SDK1.3환경에서 구현 및 실행하였다.

• Progress in Superconductivity
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• v.7 no.2
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• pp.120-129
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• 2006

We comparatively studied the epitaxial growth conditions of $CeO_2$ and $Y_2O_3$ thin buffers on textured Ni tapes using rf magnetron sputtering and investigated the feasibility of getting a single mixture layer or sequential layers of $CeO_2$ and $Y_2O_3$ for more simplified buffer architecture. All the buffer layers were first deposited using the reducing gas of $Ar/4%H_2$ and subsequently the reactive gas mixture of Ar and $O_2$, The crystalline quality and biaxial alignment of the films were investigated using X-ray diffraction techniques (${\Theta}-2{\Theta},\;{\phi}\;and\;{\omega}\;scans$, pole figures). The $CeO_2$ single layer exhibited well developed (200) epitaxial growth at the condition of $10%\;O_2$ below an $450^{\circ}C$, but the epitaxial property was decreased with increasing the layer thickness. $Y_2O_3$ seldom showed optimum condition for (400) epitaxial growth. The sequential architecture of $CeO_2/Y_2O_3/CeO_2$ having good epitaxial property was achieved by sputtering at a temperature of $700^{\circ}C$ on the initial $CeO_2$ bottom layer sputtered at $400^{\circ}C$. Cracking of the sputtered buffer layers was seldom observed except the double layer structure of $CeO_2/Y_2O_3$.

• Journal of the Korean Institute of Rural Architecture
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• v.12 no.2
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• pp.49-58
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• 2010

This study is to clarify the actual condition of some characteristics of a public facilities and the space design of laube of Japanese 3-Kleingartens. The results of this paper is as follows: 1)There are basically all the public facility for maintenance in the kleingartens. B and C Kleingartens have the various public facilities to get the additional experience for members. 2) All the laube is a wood structure, the floor plans are all the same square types. The deck, terrace, and balcony were very useful facilities to agricultural works. 3)The basic rooms of all the laube are usual entry, storage, kitchen, dining, living, bathroom. The floor plan of A and B laube is planned by a closed kitchen, C laube is a living kitchen. The living room of B laube is a variable space, to separating or unity room possibly.

• Proceedings of the CALSEC Conference
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• 2003.09a
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• pp.261-267
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• 2003

This study deals with controversial issues surrounding the today′s cyber-taxation and recommends feasible consumption tax system architecture titled Global Electronic Tax Invoice System (GETI). The GETI is an electronic consumption tax architecture to provide "all-in-one" tax and e-payment services through a trusted third party (TTP). GETI is designed to streamline the overall cyber-taxation process and provide simplified and transparent tax invoice services through an authorized np. To ensure information security, GETI incorporates public Key infrastructure (PKI) based digital certificates and other data encryption schemes when calculating, reporting, paying, and auditing tax in the electronic commerce environment. GETI is based on the OECD cyber-taxation agreement that was reached in January 2001, which established the taxation model for B2B and B2C electronic commerce transactions. For the value added tax systems, tax invoice is indispensable to commerce activities, since they provide documentations to prove the validity of commercial transactions. As paper-based tax invoice systems are gradually phased out and are replaced with electronic tax invoice systems, there is an increasing need to develop a reliable, efficient, transparent, and secured cyber-taxation architecture. To design such architecture, several desirable system attributes were considered -- reliability, efficiency, transparency, and security. GETI was developed with these system attributes in mind.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.6
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• pp.18-26
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• 1999

This paper presents the architecture and design of a DSSS MODEM ASIC chip for wireless local area networks (WLAN). The implemented MODEM chip supports the DSSS physical layer specifications of the IEEE 802.11. The chip consits of a transmitter and a receiver which contain a CRC encoder/decoder, a differential encoder/decoder, a frequency offset compensator and a timing recovery circuit. The chip supports various data rates, i.e., 4,2 and 1Mbps and provides both DBPSK and DQPSK for data modulation. We have performed logic synthesis using the $SAMSUNG^{TM}$ $0.6{\mu}m$ gate array library and the implemented chip consists of 53,355 gates. The MODEM chip operates at 44MHz, the package type is 100-pin QFP and the power consumption is 1.2watt at 44MHz. The implemented MODEM architecture shows lower BER compared with the Harris HSP3824.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.39-47
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• 1998

This paper describes high-speed pipelined memory architecture for a shared buffer ATM switch. The memory architecture provides high speed and scalability. It eliminates the restriction of memory cycle time in a shared buffer ATM switch. It provides versatile performance in a shared buffer ATM switch using its scalability. It consists of a 2-D array configuration of small memory banks. Increasing the array configuration enlarges the entire memory capacity. Maximum cycle time of the designed pipelined memory is 4 ns with 5 V V$\_$dd/ and 25$^{\circ}C$. It is embedded in the prototype chip of a shared scalable buffer ATM switch with 4 x 4 configuration of 4160-bit SRAM memory banks. It is integrated in 0.6 $\mu\textrm{m}$ 2-metal 1-poly CMOS technology.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.388-390
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• 2006

This paper presents a hybrid SoC design for phase detection of single tone signal. The designed hybrid SoC is composed of three functional blocks, i.e., an analog to digital converter module, a phase detection module and a controller module. A design of the controller module is based on a 16-bit RISC architecture. An I/O interface and an LCD control interface for transmission and display of phase measurement values are included in the design of the controller module. A design of the phase detector is based on a recursive sliding-DFT. The recursive architecture effectively reduces the gate numbers required in the implementation of the module. The ADC module includes a single-bit second-order sigma-delta modulator and a digital decimation filter. The decimation filter is designed to give 98dB of SNR for the ADC. The effective resolution of the ADC is enhanced to 98dB of SNR by the incorporation of a pre FIR filter, a 2-stage cascaded integrator- comb(CIC) filter and a 30-tab FIR filter in the decimation. The hybrid SoC is verified in FPGA and implemented in 0.35 CMOS Technology.