• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.291-291
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• 2011

플라즈마에 노출된 재료 표면의 온도 증가는 다음과 같은 요인에 의해서 결정된다. 이온의 충돌에 의한 역학적 에너지, 이온의 중성화, 라디칼의 안정화에 의한 에너지 방출(잠열, latent heat), 플라즈마에서 방출된 빛의 흡수. 이중 식각을 위한 기판 바이어스에 의해서 주로 결정되는 이온 충돌 에너지와 잠열의 방출이 300 mm wafer용 유도 결합 플라즈마 식각 장치에서 소스 전력과 바이어스 전력에 따라서 어떻게 변화하는지 전산 유체 역학 모사 프로그램인 CFD-ACE를 이용하여 상용 식각 장비인 AMAT사의 DPS II를 대상으로 온도 분포의 변화를 계산하였다. 실험 결과와 비교를 위하여 다섯 곳에(상, 하, 좌, 우, 중심) 열전대를 부착한 온도 측정 웨이퍼를 기판의 위치에 설치하고 여러 가지 실험 조건에 대해서 온도의 변화를 측정하였다. Ar 10 mTorr에서 2열 병렬 안테나의 전력을 300 W에서 시간에 따른 온도의 변화를 측정하였다. 이때 wafer의 평균 온도는 $28.9^{\circ}C$에서 $150^{\circ}C$까지 12분 내에 상승하였으며 최고 온도에 도달한 다음에는 거의 일정하게 유지 되었다. Si의 식각에서 온도의 영향을 가장 크게 받는 반응은 F 라디칼에 의한 Si의 직접 식각이며 Arrhenius 식의 형태로 표현하면 0.116*exp (-1250/T)의 형태로 된다. 문헌에 보고된 계수를 이용해서 $29^{\circ}C$의 식각 속도와 플라즈마에 의한 가열 최고 온도인 $150^{\circ}C$ 때의 값을 비교해보면 3.3배의 차이가 난다. 따라서 4%내의 식각 균일도를 목표로 하는 폴리 실리콘 게이트 식각 장비의 설계에서는 플라즈마에 의한 가열 불균일을 상쇄 할 수 있는 히터와 냉각 구조의 최적 설계가 필요하다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.1
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• pp.73-79
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• 2013

Crystalline silicon solar cells with $SiN_x/SiN_x$ and $SiN_x/SiO_x$ double layer anti-reflection coatings(ARC) were studied in this paper. Optimizing passivation effect and optical properties of $SiN_x$ and $SiO_x$ layer deposited by PECVD was performed prior to double layer application. When the refractive index (n) of silicon nitride was varied in range of 1.9~2.3, silicon wafer deposited with silicon nitride layer of 80 nm thickness and n= 2.2 showed the effective lifetime of $1,370{\mu}m$. Silicon nitride with n= 1.9 had the smallest extinction coefficient among these conditions. Silicon oxide layer with 110 nm thickness and n= 1.46 showed the extinction coefficient spectrum near to zero in the 300~1,100 nm region, similar to silicon nitride with n= 1.9. Thus silicon nitride with n= 1.9 and silicon oxide with n= 1.46 would be proper as the upper ARC layer with low extinction coefficient, and silicon nitride with n=2.2 as the lower layer with good passivation effect. As a result, the double layer AR coated silicon wafer showed lower surface reflection and so more light absorption, compared with $SiN_x$ single layer. With the completed solar cell with $SiN_x/SiN_x$ of n= 2.2/1.9 and $SiN_x/SiO_x$ of n= 2.2/1.46, the electrical characteristics was improved as ${\Delta}V_{oc}$= 3.7 mV, ${\Delta}_{sc}=0.11mA/cm^2$ and ${\Delta}V_{oc}$=5.2 mV, ${\Delta}J_{sc}=0.23mA/cm^2$, respectively. It led to the efficiency improvement as 0.1% and 0.23%.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.12 no.4
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• pp.178-183
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• 2002

The PLZT (x/50/50, x = 1, 2, 5, 7) thin films have been prepared by a sol-gel method using polypropanediol as a solvent, and their dielectric properties have been investigated. The prepared sol was coated 10 times on $Pt/Ti/SiO2_2$/Si wafer. After post-annealing at 560~$600^{\circ}C$ for 10 min, the 600 nm-thick PLZT (x/50/50) thin films were formed with pure perovskite phase. Grain size of the PLZT (x/50/50) thin films was increased with increasing the amount of La. For all the compositions, dielectric properties such as dielectric constant and remnant polarization were enhanced with increasing annealing temperatures. As the amount of La was increased, the remnant polarization, coercive field and dielectric constant of the PLZT (x/50/50) thin films fired at $600^{\circ}C$ were decreased.

• Electrical & Electronic Materials
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• v.9 no.1
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• pp.30-37
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• 1996

Previously, crystallization of a-Si:H films on glass substrates were limited to anneal temperature below 600.deg. C, over 10 hours to avoid glass shrinkage. Our study indicates that the crystallization is strongly influenced by anneal temperature and weakly affected by anneal duration time. Because of the high temperature process and nonconducting substrate requirements for poly-Si TFTs, the employed substrates were limited to quartz, sapphire, and oxidized Si wafer. We report on poly-Si TFT's using high temperature anneal on a Si:H/Mo structures. The metal Mo substrate was stable enough to allow 1000.deg. C anneal. A novel TFT fabrication was achieved by using part of the Mo substrate as drain and source ohmic contact electrode. The as-grown a-Si:H TFT was compared to anneal treated poly-Si TFT'S. Defect induced trap states of TFT's were examined using the thermally stimulated current (TSC) method. In some case, the poly-Si grain boundaries were passivated by hydrogen. A-SI:H and poly-Si TFT characteristics were investigated using an inverted staggered type TFT. The poly -Si films were achieved by various anneal techniques; isothermal, RTA, and excimer laser anneal. The TFT on as grown a-Si:H exhibited a low field effect mobility, transconductance, and high gate threshold voltage. Some films were annealed at temperatures from 200 to >$1000^{\circ}C$ The TFT on poly-Si showed an improved $I_on$$I_off$ ratio of $10_6$, reduced gate threshold voltage, and increased field effect mobility by three orders. Inverter operation was examined to verify logic circuit application using the poly Si TFTs.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.593-596
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• 1999

This paper presents a process optimization of antireflectiun (AR) coating on crystalline Si solar cells. Theoretical and experimental investigations were performed on a doble-layer AR(DLAR) coating of MgF$_2$/CeO$_2$, We investigated CeO$_2$ films as an All layer because they hale a proper refractive index of 2.46 and demonstrate the same lattice constant as Si substrate. RF sputter grown CeO$_2$ film showed strong dependence on a deposition temperature. The CeO$_2$ film deposited at 400 $^{\circ}C$ exhibited a strong (111) preferred orientation and the lowest surface roughness of 6.87 $\AA$. Refractive index of MgF$_2$ film was measured as 1.386 for the most of growth temperature. An optimized DLAR coating showed a reflectance as low as 2.04 % in the wavelengths ranged from 0.4 7m to 1.1 7m. We achieved the efficiencies of solar cells greater than 15% with 3.12 % improvement with DLAR coatings . Further details on MgF$_2$, CeO$_2$ films, and cell fabrication Parameters are presented in this paper.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.11
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• pp.35-43
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• 1995

To obtain high quality of $Ta_{2}O_{5}$ film, two dielectric layers of $Si_{3}N_{4}$ and $Ta_{2}O_{5}$ were subsequently formed on Si wafer. Silicon nitride films were thermally grown in 10 Torr ammonia ambient by R.F induced heating system. The thickness of thermally grown $Si_{3}N_{4}$ film was able to be controlled in the range of tens $\AA$ due to the self-limited growth property. $Ta_{2}O_{5}$ film of 200$\AA$ thickness was then deposited on the as-grown $Si_{3}N_{4}$ film about 25$\AA$ thickness by sputtering method and annealed at $900^{\circ}C$in $O_{2}$ ambient for 1hr. Stoichiometry film was prepared by the annealing in oxygen ambient. Despite the high temperature anneal process, silicon oxide layer was not grown at the interface of the layered films because of the oxidation barrier effect of Si$_{3}$N$_{4}$ film. The fabricated $Ta_{2}O_{5}$/$Si_{3}N_{4}$ film showed low leakage current less than several nA and high dielectric breakdown strength.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.6
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• pp.514-519
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• 2000

This paper describes on the temperature characteristics of a SDB(silicon-wafer direct bonding) SOI(silicon-on-insulator) Hall sensor. Using the buried oxide $SiO_2$as a dielectrical isolation layer a SDB SOI Hall sensor without pn junction has been fabricated on the Si/ $SiO_2$/Si structure. The Hall voltage and the sensitivity of the implemented SOI Hall sensor show good linearity with respect to the applied magnetic flux density and supplied current. In the temperature range of 25 to 30$0^{\circ}C$ the shifts of TCO(temperature coefficient of the offset voltage) and TCS(temperature coefficient of the product sensitivity) are less than $\pm$6.7$\times$10$_{-3}$ and $\pm$8.2$\times$10$_{-4}$$^{\circ}C$ respectively. These results indicate that the SDB SOI structure has potential for the development of a silicon Hall sensor with a high-sensitivity and high-temperature operation.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.03a
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• pp.99-99
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• 2003

The growth of GaN on Si is of great interest due to the several advantages : low cost, large size and high-quality wafer availability as well as its matured technology. The crystal quality of GaN is known to be much influenced by the surface pretreatment of Si substrate[1]. In this work, the properties of GaN overlayer grown on ion beam modified Si(111) have been investigated. Si(111) surface was treated RIB with 1KeV-N$_2$$\^$+/(at 1.9 ${\times}$ 10$\^$-5/) to dose ranging from 5${\times}$10$\^$15/ to 1${\times}$10$\^$17/ prior to film growth. GaN epilayers were grown at 1100$^{\circ}C$ for 1 hour after growing AlN buffer layers for 5∼30 minutes at 1100$^{\circ}C$ in Metal Organic Chemical Vapor Deposition (MOCVD). The properties of GaN epilayers were evaluated by X-Ray Diffraction(XRD), Raman spectroscopy, Photoluminescence(PL) and Hall measurement. The results showed that the ion modified treatment markedly affected to the structural, optical and electrical characteristic of GaN layers.

• Transactions of the Society of Information Storage Systems
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• v.1 no.2
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• pp.182-187
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• 2005

A large area micro mirror is an optical element that functions as changing an optical path by reflection in integrated optical system. We fabricated the large area silicon mirror by anisotropic etching using MEMS for implementation of integrated optical pickup. In this work, we report the optimum conditions to better fabricate and design, greatly improve mirror surface quality. To obtain mirror surface of $45^{\circ},\;9.74^{\circ}$ off-axis silicon wafer from (100) plane was used in etching condition of $80^{\circ}C$ with 40wt.% KOH solution. After wet etching, polishing process by MR fluid was applied to mirror surface for reduction of roughness. In the next step, after polymer coating on the polished Si wafer, the Si mirror was fabricated by UV curing using a trapezoid bar-type way structure. Finally, we obtained peak to valley roughness about 50 nm in large area of $mm^2$ and it is applicable to optical pickup using blu-ray wavelength as well as infrared wavelength.

• Journal of the Korean institute of surface engineering
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• v.28 no.4
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• pp.225-235
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• 1995

To investigate the effects of pretreatment and substrate bias on the characteristics of the diamond thin films, the thin films were deposited on the p-type Si(100) wafer by MPECVD using mixtures of $H_2$, $CH_4$, and $O_2$ gases. Deposition was carried out at the substrate temperature of $900^{\circ}C$ and at the pressure of 40torr. The effect of the pretreatment on the film formation was the examined by using SiC and diamond powders as abrasive powders. Furthermore, the substrate bias effect on the formation of the diamond film was also examined. The highest nucleation density was observed for the pretreatment with 40~60$\mu\textrm{m}$ size of diamond powders and a negative bias potential(-50V). Many defects and(111) twins in the diamond films were observed.