• Title/Summary/Keyword: C-language

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SystemVerilog-based Verification Environment using SystemC Constructs (SystemC 구성요소를 이용한 SystemVerilog 기반 검증환경)

  • Oh, Young-Jin;Song, Gi-Yong
    • Journal of the Institute of Convergence Signal Processing
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    • v.12 no.4
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    • pp.309-314
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    • 2011
  • As a system becomes more complex, a design relies more heavily on a methodology based on high-level abstraction and functional verification. SystemVerilog includes characteristics of hardware design language and verification language in the form of extensions to the Verilog HDL. However, the OOP of System Veri log does not allow multiple inheritance. In this paper, we propose adoption of SystemC to introduce multiple inheritance. After being created, a SystemC unit is combined with a SystemVerilog-based verification environment using SystemVerilog DPI and ModelSim macro. Employing multiple inheritance of SystemC makes a design of a verification environment simple and easy through source code reuse. Moreover, a verification environment including SysemC unit has a benefit of reconfigurability due to OOP.

System Design of 900MHz RFID Eucational System including the Active Tag (능동형 태그를 포함한 900MHz RFID 교육용 시스템의 설계)

  • Kim, H.C.;Ohlzahas, A.;Kim, J.M.;Jin, H.S.;Cho, D.G.;Chung, J.S.;Kang, O.H.;Jung, K.W.
    • Journal of Internet Computing and Services
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    • v.8 no.4
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    • pp.51-59
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    • 2007
  • This paper presents the development of RFID educational system based on using 900MHz air interface between the reader and the active tag. The software of reader and the active tag is developed on embedded environment, and the software of PC controlling the reader is based on window OS operated as the server. The AT89C51ED2 VLSI chip is used for the processor of the reader and the active tag. As the development environment, Keil compiler is used for the reader and the active tag of which the programing language is C. The visual C language of the visual studio on the PC activated as the server is used for development language. To verify the function of the system, PC gets the tag's identification number through the reader and send the data to with the active tag memory a certain contents as "wite" operation. Finally the data written from the active tag's memory is sent to the PC via the reader as "read" operation and compare the received data with one already sent to the tag.

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Study on Tree-Structured Database and Language MUMPS (트리형 데이터베이스 및 언어 MUMPS 활용)

  • Im, Ji-Hyeon;Kim, Jin-Doeg
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2019.05a
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    • pp.108-110
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    • 2019
  • A Database is a collection of data that does not have redundancy, and it is essential to easily use and share information in an information society where the amount of information is increasing. A typical structure of a Database is a relational database and a tree-structure Database. This research studies the programming language MUMPS, which is a tree structure database. This language constructs the database by storing arrays in a dynamic or B-Tree format. Unlike SQL, which must be used in languages such as Java and C #, MUMPS supports language and database independently and can manage data, so the data porting rate is high. In fact, in U.S. hospitals, the MUMPS-based platform has a high market share.

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Where a Null C Fails to PF-merge

  • Hong, Sung-Shim
    • Language and Information
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    • v.9 no.2
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    • pp.69-83
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    • 2005
  • This paper discusses the distribution of a null complementizer C, as opposed to an overt counterpart 'that', presenting empirical support both for and against the PF-merge analysis of C proposed by Boscovic and Lasnik (2003, henceafter B&L) who in turn attribute to the proposal in Pesetsky (1992) and Halle & Marantz (1993). In Section I, as a background, I discuss B&L's proposal that a null complementizer C is a PF-affix which undergoes a PF-merger operation at the PF component. In Section 2, after a brief sketch of the distribution of a null C mostly in bare-relatives, I explore the possibility of extending B&L's analysis to accomodate the null C's in the bare-relative constructions. In Section 3, I argue that despite some empirical difficulties, B&L's analysis of a null C as a PF-affix can still be maintained, if Adverb Fronting is an operation to Spec-C position. Furthermore, I propose a rule - PF Spell-Out Constraint - to account for the C-trace (i.e. that-trace) effect in relative constructions. With the PF Spell-Out Constraint and B&L's PF-merge account, the distribution of a null C can better be analyzed.

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Analysis of Multiple Intelligences and Academic Adjustment Level for Undergraduate Students of IT Major -Focused on C Programming- (IT 학부생의 다중지능과 학문적 적응도 분석 -C 프로그래밍을 중심으로-)

  • Yoo, Sang-Mi;Choi, Byongsu
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.14 no.6
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    • pp.189-197
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    • 2014
  • This study analyzed the characteristics of multiple intelligence and the levels of academic adjustment for the department and the major among undergraduate students majoring in IT. Seventy freshmen majoring in IT at the department of M, H University participated in this study and the basic major subject required for the department was Computer Language: I-C Language. Eight intelligence areas less controversial in Gardner's multiple intelligence theory were used; academic adjustment was manipulatively defined as the degree of adjustment for the department and the major among undergraduate students; and pleasure, flow, familiarity and relevance to the major, academic achievement, and major satisfaction were selected as variables through literature review. The undergraduate students majoring in IT showed high levels of interpersonal intelligence and intrapersonal intelligence, with insignificant gender differences. Significant correlations were found between multiple intelligence and academic adjustment. In particular, while pleasure and flow in C programming were found to be at low levels in academic adjustment, the significant correlation between linguistic intelligence in multiple intelligence and flow in C language was a very interesting finding. While significant correlation was not found between multiple intelligence and academic achievement, students who were more highly aware of the relevance to the major and who were more familiar with C language showed higher academic achievement. Lastly, limitations of this study were discussed; on the basis of the results, suggestions were made about prescriptive strategies to improve academic achievement for undergraduate students majoring in IT.

Word Embedding using word position information (단어의 위치정보를 이용한 Word Embedding)

  • Hwang, Hyunsun;Lee, Changki;Jang, HyunKi;Kang, Dongho
    • Annual Conference on Human and Language Technology
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    • 2017.10a
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    • pp.60-63
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    • 2017
  • 자연어처리에 딥 러닝을 적용하기 위해 사용되는 Word embedding은 단어를 벡터 공간상에 표현하는 것으로 차원축소 효과와 더불어 유사한 의미의 단어는 유사한 벡터 값을 갖는다는 장점이 있다. 이러한 word embedding은 대용량 코퍼스를 학습해야 좋은 성능을 얻을 수 있기 때문에 기존에 많이 사용되던 word2vec 모델은 대용량 코퍼스 학습을 위해 모델을 단순화 하여 주로 단어의 등장 비율에 중점적으로 맞추어 학습하게 되어 단어의 위치 정보를 이용하지 않는다는 단점이 있다. 본 논문에서는 기존의 word embedding 학습 모델을 단어의 위치정보를 이용하여 학습 할 수 있도록 수정하였다. 실험 결과 단어의 위치정보를 이용하여 word embedding을 학습 하였을 경우 word-analogy의 syntactic 성능이 크게 향상되며 어순이 바뀔 수 있는 한국어에서 특히 큰 효과를 보였다.

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VHDL Implementation of an LPC Analysis Algorithm (LPC 분석 알고리즘의 VHDL 구현)

  • 선우명훈;조위덕
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.32B no.1
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    • pp.96-102
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    • 1995
  • This paper presents the VHSIC Hardware Description Language(VHDL) implementation of the Fixed Point Covariance Lattice(FLAT) algorithm for an Linear Predictive Coding(LPC) analysis and its related algorithms, such as the forth order high pass Infinite Impulse Response(IIR) filter, covariance matrix calculation, and Spectral Smoothing Technique(SST) in the Vector Sum Exited Linear Predictive(VSELP) speech coder that has been Selected as the standard speech coder for the North America and Japanese digital cellular. Existing Digital Signal Processor(DSP) chips used in digital cellular phones are derived from general purpose DSP chips, and thus, these DSP chips may not be optimal and effective architectures are to be designed for the above mentioned algorithms. Then we implemented the VHDL code based on the C code, Finally, we verified that VHDL results are the same as C code results for real speech data. The implemented VHDL code can be used for performing logic synthesis and for designing an LPC Application Specific Integrated Circuit(ASOC) chip and DsP chips. We first developed the C language code to investigate the correctness of algorithms and to compare C code results with VHDL code results block by block.

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KorQATeC2.0: Construction of Test Collection for Evaluation of Question Answering System (KorQATeC2.0: 질의/응답 시스템의 성능 평가를 위한 평가집합 구축)

  • Kim, Jae-Ho;Lee, Kyung-Soon;Oh, Jong-Hoon;Chang, Du-Seong;Choi, Key-Sun
    • Annual Conference on Human and Language Technology
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    • 2001.10d
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    • pp.397-404
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    • 2001
  • 본 논문에서는 질의/응답 시스템의 평가를 위해 구축된 평가집합 (Korean Question Answering Test Collection 2.0: KorQATeC2.0)에 대하여 기술한다. KorQATeC2.0은 총 120개의 질의와 207,067개의 문서로 구성되어 있으며, 120개의 질의는 질의에 대한 정답을 제시하는 방식에 따라 기본 과제 질의, 나열 과제 질의, 문맥 과제 질의, 요약 과제 질의로 나누어진다. 또한 KorQATeCl.0과는 달리 여러 문서를 참조하여 정답을 구성하는 질의와 문서집합에 정답이 존재하지 않는 질의를 포함시킴으로써 질의/응답 시스템의 평가를 다양하게 할 수 있도록 하였다. 본 논문에서 기술하는 평가집합은 질의/응답 시스템의 객관적 평가를 가능하게 한다는 점에서 그 의의가 있다.

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Feature Extraction for Community Question Answering System(cQA) considering Question Characteristic (질문 특성을 고려한 커뮤니티 질의응답 시스템(cQA) 자질 추출 방법)

  • Park, Yongmin;Kim, Bogyum;Lee, Jae Sung
    • Annual Conference on Human and Language Technology
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    • 2014.10a
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    • pp.119-121
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    • 2014
  • 커뮤니티 질의응답 시스템(cQA)은 기존에 구축된 '질문-답' 쌍에서 사용자의 질문과 비교하여 유사도 순으로 결과를 보여주는 시스템이다. 본 논문에서는 '국립국어원'의 질의응답 게시판에 적용 가능한 '커뮤니티 질의응답 시스템'을 소개하고, 국립국어원 질의응답 게시판의 질문 특성을 분석하여 cQA의 성능 향상을 위한 자질 추출 방법을 제시한다.

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(Design of GF(216) Serial Multiplier Using GF(24) and its C Language Simulation (유한체 GF(24)를 이용한 GF(216)의 직렬 곱셈기 설계와 이의 C언어 시뮬레이션)

  • 신원철;이명호
    • Journal of the Korea Society of Computer and Information
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    • v.6 no.3
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    • pp.56-63
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    • 2001
  • In this paper, The GF(216) multiplier using its subfields GF(24) is designed. This design can be used to construct a sequential logic multiplier using a bit-parallel multiplier for its subfield. A finite field serial multiplier using parallel multiplier of subfield takes a less time than serial multiplier and a smaller complexity than parallel multiplier. It has an advatageous feature. A feature between circuit complexity and delay time is compared and simulated using C language.

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