• The Transactions of the Korea Information Processing Society
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• v.3 no.5
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• pp.1346-1353
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• 1996

In this paper, we propose a modeling method for the flip-flops and test generation algorithms to detect the faults in the sequential circuits using VHDL in the high-level design environment. RS, JK, D and T flip-flops are modeled using data flow types. The sequence of micro-operation which is the basic structure of a chip-level leads to a control point where varnishing occurs to one of two micro- operation sequence. In order to model the fault of one micro-operation(FMOP) that perturb another micro-operation effectively, the concept of goal trees and some heuristic rules are used. Given a faulty FMOP or fault of control point (FCON), a test pattern is generated by fault sensitization, path sensitization and determination of the imput combinations that will justify the path sensitization. The fault models are restricted to the data flow model in the ARCHITECTURE statement of VHDL. The proposed algorithm is implemented in the C language and its efficiency is confirmed by some examples.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.4 s.37
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• pp.281-287
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• 2005

in-situ electromigration test was carried out for edge drift lines of eutectic SnPb solder using Scanning Electron Microscopy (SEM). The electromigration test for the eutectic SnPb solder sample was conducted at temperature of $90^{\circ}C$ and the current density of $6{\times}10^4A/cm^2$. Edge drift at cathode and hillock growth at anode were observed in-situ in a SEM chamber during electromigration test. It was clearly revealed that eutectic SnPb solder lines has an incubation stage before void formation during electromigration test, which seemed to be related to the void nucleation stage of flip chip solder electromigration behaviors.

• Journal of IKEEE
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• v.14 no.1
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• pp.1-7
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• 2010

This paper presents an implementation of the DisplayPort AUX(Auxiliary) Channel. DisplayPort uses Main link, AUX Channel and Hot Plug Detect line to transfer the video & audio data. For isochronous transport service, source device converts to image and audio data which are to be transported through the Main Link and transports the restructured image and audio data to sink device. The AUX Channel provides link service and device service for discovering, initializing and maintaining the Main link. Hot Plug Detect line is used to confirm the connection between source device and sink device. The AUX Channel is implemented with 3315 LUTs(Look Up Table), 1466 Flip Flops and 168.782MHz max speed synthesized using Xilinx ISE 9.2i at SoC Master3.

• Transactions on Electrical and Electronic Materials
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• v.17 no.4
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• pp.196-200
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• 2016

We have developed new electrostatic discharge (ESD) protection devices with, bidirectional flip chip transient voltage suppression. The devices differ in their epitaxial (epi) layers, which were grown by reduced pressure chemical vapor deposition (RPCVD). Their ESD properties were characterized using current-voltage (I-V), capacitance-voltage (C-V) measurement, and ESD analysis, including IEC61000-4-2, surge, and transmission line pulse (TLP) methods. Two BD-FCTVS diodes consisting of either a thick (12 μm) or thin (6 μm), n-Si epi layer showed the same reverse voltage of 8 V, very small reverse current level, and symmetric I-V and C-V curves. The damage found near the corner of the metal pads indicates that the size and shape of the radius governs their failure modes. The BD-FCTVS device made with a thin n- epi layer showed better performance than that made with a thick one in terms of enhancement of the features of ESD robustness, reliability, and protection capability. Therefore, this works confirms that the optimization of device parameters in conjunction with the doping concentration and thickness of epi layers be used to achieve high performance ESD properties.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1556-1559
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• 1987

In this paper, a new state assignment method is proposed for the implementation of the area-effective control part. Introducing the, concept of adjacency matrix to control table generated by SDL(Symbolic Description Language) hardware compiler, a state assignment method is proposed with which minimal number of flip flops and effective number of product terms can be obtained to accomplish the area-effective implementation. Also, with substituting the assigned code to state transition table, boolean equations are obtained through 2-level logic minimization. Proposed algorithm is programmed in C-language on VAX-750/UNIX and b efficiency is shown by the practical example.

• Proceedings of the KWS Conference
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• 2007.11a
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• pp.146-149
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• 2007

1) 자체 제작한 NCP인 A, B, C 3종은 상용화 제품에 비해 도포성에 관련한 특성은 우수한 것으로 나타났으나 Tg 등의 열특성은 개선이 필요한 것으로 판단된다. 2) 접합강도의 경우 4종의 큰 차이가 없었으나 필러가 비교적 적은 조성인 B 조성의 경우 가장 큰 접합강도를 나타냈다. 3) NCP A, B, C 3종에 대한 접속저항 측정 결과 필러가 가장 많은 C의 경우가 가장 높은 저항 값을 보였으며 이는 가속 고온 고습 시험에 대한 결과에서도 급격한 접속률 감소를 통해 확인할 수 있다. 4) 시간에 따른 접속저항의 급격한 증가는 NCP 성분 중 친수성을 가진 물질이 있는 것이 원인이라 판단되며 이에 대한 개선을 통해 고습에 대한 신뢰성을 향상시킬 수 있을 것으로 보인다.

• Proceedings of the KSME Conference
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• 2008.11b
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• pp.2750-2753
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• 2008

This paper introduce the CFD analysis for predicting the heat transfer at the Ultrasonic horn. Approximately Ultrasonic horn separates two part. One is preheating part and the other is cooling part. Temperature of preheating part rise up by $260^{\circ}C$ that make it possible to attach a chip to a semiconductor. Also there is a piezo material in the cooling part. When piezo work, it generates heat of $100^{\circ}C$. It can stand by $150^{\circ}C$. But the high temperature conducted from the preheating part has a bad affect on the piezo. These situation make it necessary cooling at piezo. Previously except of the piezo, all of them are composed of the SUS440c that has good thermal conductivity. This study shows way that not only cooling the piezo but also cutting off the conduction between preheating part and cooling part by using the Ti and Duralumin that have low thermal conductivity compare with the SUS440c. Conclusion of CFD analysis that the heat coming from the piezo can't be transferred the horn cause of the Ti and Duralumin.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1507-1511
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• 1987

This paper proposes a NAND-NAND logic sequential Programmable Logic Array (PLA) using CMOS technology, and test generation methods about stuck-open faults. By using LSSD (Level Sensitive Scan Design) method instead of Flip-Flops in Sequential PLA, the complex test problems of sequential logic are simplified. After generating the test sets using connection graph, regular test sequences and all transistor faults detection method in PLA are proposed. Finally, by programming these algorithms in PASCAL at VAX 8700 and adopting these to pratical CMOS Sequential PLA circuits, we proved the effectiveness of this design.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.3
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• pp.267-271
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• 2004

The joint strength and fracture surface of Sn-Pb solder bump in photo diode packages after isothermal aging testing were studied experimentally. Cu/Sn-Pb solders were adopted, and aged for up to 900 hours at 12$0^{\circ}C$ and 17$0^{\circ}C$ to analyze the effect of intermetallic compound(IMC). In 900-hour aging experiments, the maximum shea strength of Sn-Pb solder decreased by 20％ and 9％. The diffraction patterns of Cu$_{6}$Sn$_{5}$, scallop-shape IMC, and planar-shape Cu$_3$Sn were observed by Transmission Electron Microscopy (TEM).EM).

• 한국초전도학회:학술대회논문집
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• v.9
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• pp.48-53
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• 1999

We demonstrate small-scale high-T$_c$ superconductor RSFQ(Rapid Single Flux Quantum) circuits using multilayer bicrystal technology. An RSFQ balanced comparator is demonstrated with good current resolution, and its operating conditions are discussed in some detail. A single-loop delta-sigma modulator is realized adding a feedback loop to the comparator. The effect of the feedback is confirmed by dc measurement and simulation. A design of an RSFQ toggle flip-flop with the same multilayer bicrystal technology is suggested.