• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.13 no.3
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• pp.64-72
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• 1999

The fictitious power theory in time domain is very easy to understand, but power analyzing speed of active power is increased, because power is analyzed using signal tedmiques based on the corre1ation between voltage and current wavefonns. Also, conventional methods in time/frequency domain to evaluate the correlation performance of active power filters are not provided easy solutions. So, the authors have previously proposed 3-D current coordinates which is composed into active component, fundarrental reactive component and distorted component of nonlinear loads current. This trethod has excellent perfonnance, but can not evaluate the characteristics of nonlinear load current whether It is inductive or capacitive. Therefore, To overcorre problems trentioned previously, this paper deals with the simple average power theory and the modified 3-D current coordinates for evaluating the compensation perfonnance of active power filters. To confirm the validity, active power filter simulator is developed using C-language. From the simulation, results are discussed their utility.tility.

• Journal of Broadcast Engineering
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• v.5 no.2
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• pp.211-219
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• 2000

The IBAC DAB system was interfered by existing FM broadcasting signal as was used guardband within existing FM broadcasting. The FM interference signals are very important parameter in performance evaluation of IBAC DAB system. We got the characteristic of FM PSD in according to instantaneous change and average characteristic of FM broadcasting signal in according to characteristic of FM channel. In this paper, based on proposed IBAC DAB system, we analyze effects of FM interference for occupied bandwidth and performance of IBAC DAB modeling various FM interference signals with sum of sinusoid function using C language, suggest FM interference ratio that can maintain performance. We was know that IBAC DAB system have a great performance variation in according to average characteristic of FM PSD by simulation results, also, FM interference ration that can maintain performance of system is 10dB.

• Journal of the Korean Data and Information Science Society
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• v.21 no.1
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• pp.99-107
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• 2010

This research is for implementation of a software that can convert Hangul format file to $T_EX$ format file. Hangul is a word processor that has widely been used in Korea. It is known that Hangul is relatively easy of typing in equations and tables in preparing a paper draft. $T_EX$ has been developed as a computer programming language for preparing and publishing documents. Documents are first typed in with a plain text editor with $T_EX$ commands and then is compiled and linked. The software implemented in this research converts Hangul format files which are written under the specific format of a journal to $T_EX$ format file with the given style specific file. It converts special symbols, texts, tables, equations, and paragraph formats. We have used Hangul format of Journal of the Korean Data & Information Science Society (JKDISS) and the style file of $T_EX$ for the beta-test for the software.

• International Journal of Precision Engineering and Manufacturing
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• v.4 no.5
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• pp.27-33
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• 2003

G-code, another name of ISO6983, has been a popular commanding language for operating machine tools. This G-code, however, limits the usage of today's fast evolving high-performance hardware. For intelligent machines, the communications between machine and CAD/CAM departments become important, but the loss of information during generating G-code makes the production department isolated. The new standard for operating machine tools, named STEP-NC is just about to be standardized as ISO14649. As this new standard stores CAD/CAM information as well as operation commands of CNC machines, and this characteristic makes this machine able to exchange information with other departments. In this research, the new CNC machine operated by STEP-NC was built and tested. Unlike other prototypes of STEP-NC milling machines, this system uses the STEP-NC file in XML file form as data input. This machine loads information from XML file and deals with XML file structure. It is possible for this machine to exchange information to other databases using XML. The STEP-NC milling machines in this research loads information from the XML file, makes tool paths for two5D features with information of STEP-NC, and machines automatically without making G-code. All software is programmed with Visual $C^{++}$, and the milling machine is built with table milling machine, step motors, and motion control board for PC that can be directly controlled by Visual $C^{++}$ commands. All software and hardware modules are independent from each other; it allows convenient substitution and expansion of the milling machine. Example 1 in ISO14649-11 having the full geometry and machining information and example 2 having only the geometry and tool information were used to test the automatic machining capability of this system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.6B
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• pp.1183-1190
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• 1999

This paper presents an efficient hardware architecture to improve the frame memory interface occupying the largest hardware area together with motion estimator in implementing MPEG-2 video encoder as an ASIC chip. In this architecture, the memory size for internal data buffering and hardware area for frame memory interface control logic are reduced through the efficient memory map organization of the external SDRAM having dual bank and memory access timing optimization between the video encoder and external SDRAM. In this design, 0.5 m, CMOS, TLM (Triple Layer Metal) standard cells are used as design libraries and VHDL simulator and logic synthesis tools are used for hardware design add verification. The hardware emulator modeled by C-language is exploited for various test vector generation and functional verification. The architecture of the improved frame memory interface occupies about 58% less hardware area than the existing architecture[2-3], and it results in the total hardware area reduction up to 24.3%. Thus, the (act that the frame memory interface influences on the whole area of the video encoder severely is presented as a result.

• 대한공업교육학회지
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• v.32 no.2
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• pp.199-216
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• 2007

Stream Control Transmission Protocol(SCTP) is a transport layer protocol to support the data transmission. SCTP is similar to Transmission Control Protocol(TCP) in a variety of aspects. However, several features of SCTP including multi-homing and multi-streaming incur the performance difference from TCP. This paper highlights the data transfer during the initial slow start phase in SCTP congestion control composed of slow start phase and congestion avoidance phase. In order to compare the mean transfer time between SCTP and TCP, we experiment with different performance parameters including bandwidth, round trip time, and data length. By varying data length, we also measure the corresponding initial window size, which is one of factors affecting the mean transfer time. For the experiment, we have written server and client applications by C language using SCTP socket API and have measured the transfer time by ethereal program. We transferred data between client and server using round-robin method. Analysis of these experimental results from the testbed implementation shows that larger initial window size of SCTP than that of TCP brings the reduction in the mean transfer time of SCTP compared with TCP by 15 % on average during the initial slow start phase.

• The Transactions of the Korea Information Processing Society
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• v.5 no.9
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• pp.2378-2387
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• 1998

This thesis proposes a design algorithm of an efficient space response compactor for Built-In Self-Testing of VLSI circuits. The proposed design algorithm of space compactors can be applied independently from the structure of Circuit Cnder Test. There are high hardware overhead cost in conventional space response compactors and the fault coverage is reduced by aliasing which maps faulty circuit's response to fault-free one. However, the proposed method designs space response compactors with reduced hardware overheads and does not reduce the fault coverage comparing to conventional method. Also, the proposed method can be extended to general N -input logic gate and design the most efficient space response L'Ompactors according to the characteristies of output sequence from CUT. The prolxlsed design algorithm is implemented by C language on a SUN SPARC Workstation, and some experiment results of the simulation applied to ISCAS'85 benchmark circuits with pseudo random patterns generated bv LFSR( Linear Feedback Shift Register) show the efficiency and validity of the proposed design algorithm.

• The KIPS Transactions:PartA
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• v.11A no.1
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• pp.81-88
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• 2004

In this paper, we designed the outer encoder/decoder for the terrestrial DMB that is an advanced digital broadcasting standard, implemented, and verified by using ALTERA FPGA. In the encoder part, it was created the parity bytes (16 bytes) from the input packet (188by1e) of MPEG-2 TS and the encoded data was distributed output by the convolutional interleaver for Preventing burst errors. In the decoder part, It was proposed the algorithm that detects synchronous character suitable to DMB in transmitted data from the encoder. The circuit complexity in RS decoder was reduced by applying a modified Euclid's algorithm. This system has a capability to correct error of the maximum 8 bytes in a packet. After the outer encoder/decoder algorithm was verified by using C language, described in VHDL and implemented in the ALTERA FPGA chips.

• The KIPS Transactions:PartD
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• v.15D no.3
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• pp.355-360
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• 2008

The complicated embedded system for multi-tasking requires RTOS(real-time operating system). It uses the optimal OS and processor to each embedded system on the heterogeneous development environment. This paper is proposed to use UML profile of OS API and Processor Configuration, instead of cross-compiling for developing the heterogeneous embedded system. This reduces the development time and cost through generating the automatic source code with the profile information of each embedded system. We generate and port the code after modeling the two heterogeneous real time operating systems (brickOS and uC/OS-II) and the processors (Hitachi H8 and Intel PXA255) with our proposed profile of the heterogeneous embedded system.

• Journal of KIISE:Software and Applications
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• v.29 no.12
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• pp.947-956
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• 2002

It is advantageous to use XML in developing user interfaces, since XML is independent from platforms and languages and it is easy to learn and use. The existing XML-based languages do not adopt formal model, and they are developed in ad hoc manner. Moreover, they provide limited facilities to handle user events, and combine user interface components with internal logics. In this paper, we introduce an extended MVP (EMVP) model, which is extended from MVP (Model-View-Presenter), and XUIML, which is a new XML application based on the EMVP to support user interface. XUIML provides useful methods to build user interface, including methods to describe actions on user events, data flows between objects, and internal logics. The XUIML system provides two style editors - text editor and graphic editor. It also provides two code generators. One generates Java source, and the other generate C# code from XUIML document. The XUIML graphic editor allows users to manipulate XML elements directly, and we can gain high productivity with the graphic editor.