• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.1
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• pp.61-68
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• 2017

In this paper, the coarse acquisition code (C/A code), for civil navigation, of the ranging codes for Global Positioning System (GPS) is studied, simulated and analyzed by using Matlab. We can see with the simulation results that the correctness of the method and feasibility, which is at simulation platform to further study on the real environment of GPS signal, can be confirmed. With using this results, we think, the complexity of tracking the satellite signal environment can be captured, and the performance of satellite receiver will be improved.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.3
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• pp.506-514
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• 1997

In this paper, we implement digital circuit of despreading delay lock loop for GPS receiver. The designed system consists of Epoch signal generator, two 13bit correlators which correlates the received C/A code and the locally generated C/A code in the receiver, the C/A code generator which generates C/A code of selected satellite, and the direct digital clock synthesizer which generates the clock of the C/A code generator to control the phase and clock rate, the clock controller, and the clock divider. The designed circuit has the function of the acquisition and tracking by the autocorrelation characteristics of Gold code. The controller generates each other control signals according to the correlation value. The designed circuit is simulated to verify the logic functional performance. By using the simulator STR-2770 that generates the virtual GPS signal, the deigned FPGA chip is verified the circuit performance.

• Journal of Positioning, Navigation, and Timing
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• v.4 no.4
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• pp.151-160
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• 2015

GPS L2C signal is a recently added civil signal to L2 frequency and is constructed by time division multiplexing of civil moderate (L2-CM) and civil long (L2-CL) code signals. While the L2-CM code is 20 ms-periodic and modulates satellite navigation message, the L2-CL code is 1.5s-periodic with 767,250 chips long code sequence and carries no data. Therefore, the L2-CL code signal allows receivers to perform a very long coherent integration. However, due to the length of the L2-CL code, the acquisition of the L2-CL code signal may take too long or require too much hardware resources. In this paper, we propose a three-step ultra-fast L2-CL code acquisition (TSCLA) technique for dual band GPS receivers. In the proposed TSCLA technique, a dual band GPS receiver sequentially acquires the coarse/acquisition (C/A) code signal at L1 frequency, the L2-CM code signal, and the L2-CL code signal to minimize mean acquisition time (MAT). The theoretical performance analysis and numerous Monte Carlo simulations show the significant advantage of the proposed TSCLA technique over conventional techniques introduced in the literature.

• Journal of Korea Multimedia Society
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• v.10 no.3
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• pp.411-419
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• 2007

Mounted on mobile device, set-top box, or digital TV, EVM is a virtual machine solution that can download and execute dynamic application programs. And the SIL(Standard Intermediate Language) is intermediate language of the EVM, which has a set of opcodes for object-oriented language and a sequential language. Since the C compiler used on each platform depends on the hardware, it converts C program to objective code, and then executes. To solve this problem, our research team developed ANSI C compiler and the EVM. Our ANSI C compiler outputs the SIL code based on stack machine. This paper presents the SIL-to-C decompiler in which converts the SIL code to three address code. Thus, the decompiler allows us to verify SIL code created by ANSI C compiler, and analyze a program from C language source level.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.8
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• pp.1464-1474
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• 1994

GPS(Global Positioning System)is a satellite-based navigation system that we can survey where we are, anywhere and anytime. In this paper, delay-lock loop of the receiver which detects the navigation data is theoretically analyzed, and designed using the digital logic circuit. Also logic operations for the synchronization are analyzed. The designed system consists of the correlator which correlates the received C/A code and the generated C/A code in the receiver, the C/A code generator which generates C/A code of selected satellite, and the direct digital clock syntheizer which generates the clock of the C/A code generator to control the C/A code phase and clock rate. From the analyses results of the proposed digital delay-lock loop system, the system has the detection propertied over 90% when its input signal power is above-113.98dB. The influence of input signal variation of digital delay loop, which is the input of A/D converter, is investigated and the performance is analyzed with the variation of threshold level via the computer simulation. The logic simulation results show that the designed system detects precisely the GPS navigation data.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.12
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• pp.1-8
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• 1997

In this paper, a new method of state code assignment for reduction of switching activities of state transition in asynchronous circuits is proposed. The algorithm is based on a on-hot code and modifies it to reduce switching activities. To estimate switching activities as a cost functions we introduce state transition probability (STP). AS a results, the proposed algorithm has an advantage of 60% over with the conventional code assignment in terms of switching and code length of state assignment.

• The KIPS Transactions:PartC
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• v.11C no.1
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• pp.109-114
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• 2004

A new code and its decoding scheme are proposed. With this code, we can correct and detect the errors in communication systems. To limit the runlength of data 0 and augment the minimum density of data 1, a (15, 7) BCH code is modified and an overall parity bit is added. The proposed code is a (16, 7) block code which has the bit clock signal regeneration capability and high error control capability. It is proved that the runlength of data 0 is less than or equal to 7, the density of data 1 is greater than or equal to 1/8, and the minimum Hamming distance is 6. The decoding error probability, the error detection probability and the correct decoding probability are presented for the proposed code. It is shown that the proposed code has better error control capability than the conventional schemes.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.10
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• pp.1495-1507
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• 1993

In this paper, an implementation of RS (Reed-Solomon) code decoder for CDP (Compact Disc Player) using microprogramming method is presented. In this decoding strategy, the equations composed of Newton's identities are used for computing the coefficients of the error locator polynomial and for checking the number of erasures in C2(outer code). Also, in C2 decoding the values of erasures are computed from syndromes and the results of C1(inner code) decoding. We pulled up the error correctability by correcting 4 erasures or less. The decoder contains an arithmetic logic unit over GF(28) for error correcting and a decoding controller with programming ROM, and also microinstructions. Microinstructions are used for an implementation of a decoding algorithm for RS code. As a result, it can be easily modified for upgrade or other applications by changing the programming ROM only. The decoder is implemented by the Logic Level Modeling of Verilog HDL. In the decoder, each microinstruction has 14 bits( = 1 word), and the size of the programming ROM is 360 words. The number of the maximum clock-cycle for decoding both C1 and C2 is 424.

• Journal of the Korea Society of Computer and Information
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• v.13 no.3
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• pp.45-55
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• 2008

Due to the increasing complexity of embedded system design, automatic code generation of embedded software and hardware-software co-design methodologies are gaining great interest from industries and academia. Such an automatic design methodologies are always demanding a formal system specification languages for defining designer's idea clearly and precisely. In this paper, we propose automatic embedded C code generation from SDL (Specification and Description Language, ITU-T recommended the SDL as a standard system description language) with considering a real-time uC/OS-II operating system. Our automatic embedded C code generator is expected to provide a fast specification, verification and performance evaluation platform for embedded software designs.

• 제어로봇시스템학회:학술대회논문집
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• 1996.10b
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• pp.1376-1379
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• 1996

In this paper a GPS receiver is developed using commercial chipsets. GP2010 RF front end and GP2021 Multi-channel correlator of GEC PLESSY are adapted in designing the receiver hardware. MC 68340 is used for controlling the correlator GP2021 and implementing the navigation processing. Also presented are some test results of the developed receiver whose software has an interrupt driven structure rather than common real-time kernel based structure.