• Title/Summary/Keyword: Bypass Capacitor

Search Result 13, Processing Time 0.015 seconds

Application of a C-Type Filter Based LCFL Output Filter to Shunt Active Power Filters

  • Liu, Cong;Dai, Ke;Duan, Kewei;Kang, Yong
    • Journal of Power Electronics
    • /
    • v.13 no.6
    • /
    • pp.1058-1069
    • /
    • 2013
  • This paper proposes and designs a new output filter called an LCFL filter for application to three phase three wire shunt active power filters (SAPF). This LCFL filter is derived from a traditional LCL filter by replacing its capacitor with a C-type filter, and then constructing an L-C-type Filter-L (LCFL) topology. The LCFL filter can provide better switching ripple attenuation capability than traditional passive damped LCL filters. The LC branch series resonant frequency of the LCFL filter is set at the switching frequency, which can bypass most of the switching harmonic current generated by a SAPF converter. As a result, the power losses in the damping resistor of the LCFL filter can be reduced when compared to traditional passive damped LCL filters. The principle and parameter design of the LCFL filter are presented in this paper, as well as a comparison to traditional passive damped LCL filters. Simulation and experimental results are presented to validate the theoretical analyses and effectiveness of the LCFL filter.

Power Cell-based Pulsed Power Modulator with Fast Rise Times (빠른 상승 시간을 갖는 파워 셀 기반 펄스 파워 모듈레이터)

  • Lee, Seung-Hee;Song, Seung-Ho;Ryoo, Hong-Je
    • The Transactions of the Korean Institute of Power Electronics
    • /
    • v.26 no.1
    • /
    • pp.25-31
    • /
    • 2021
  • This paper describes the design of a power cell-based pulsed power modulator with fast rise times. The pulse-generating section of the pulse power modulator is a series stack of power cells. Each power cell is composed of a storage capacitor, a pulse switch, and a bypass diode. When the pulse switches are turned on, the capacitors are connected in series and the sum of voltages is applied to the load. For output pulses with fast rise times, an IGBT with fast turn-on characteristics is adopted as a pulse switch and the optimized gate driving method is used. Pspice simulation is performed to account for the gate driving method. A 10 kV, 12-power cell-based pulsed power modulator is tested under resistive load and plasma reactor load. The rise times of output pulses less than 20 ns are confirmed, showing that the pulsed power modulator can be effectively applied to pulsed power applications with fast rise times.

Design of a Multi-Band Low Noise Amplifier for 3GPP LTE Applications in 90nm CMOS (3GPP LTE를 위한 다중대역 90nm CMOS 저잡음 증폭기의 설계)

  • Lee, Seong-Ku;Shin, Hyun-Chol
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.47 no.5
    • /
    • pp.100-105
    • /
    • 2010
  • A multi-band low noise amplifier (LNA) is designed in 90 nm RF CMOS process for 3GPP LTE (3rd Generation Partner Project Long Term Evolution) applications. The designed multi-band LNA covers the eight frequency bands between 1.85 and 2.8 GHz. A tunable input matching circuit is realized by adopting a switched capacitor array at the LNA input stage for providing optimum performances across the wide operating band. Current steering technique is adopted for the gain control in three steps. The performances of the LNA are verified through post-layout simulations (PLS). The LNA consumes 17 mA at 1.2 V supply voltage. It shows a power gain of 26 at the normal gain mode, and provides much lower gains of 0 and -6.7 in the bypass-I and -II modes, respectively. It achieves a noise figure of 1.78 dB and a IIP3 of -12.8 dBm over the entire band.