• KIPS Transactions on Computer and Communication Systems
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• v.5 no.9
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• pp.261-268
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• 2016

One of the most comfortable transportation in our day to day life is the bus, which provides real time information. In order to obtain reliable information on the arrival time of this information, BIS (Bus Information System) needs to analyse the main factor for the traffic environment. To manage the system, regional information analysis by local municipalities should be prioritized. In this paper, we analyse the features that are expected to affect traffic environment by commuting the travel to school, market, tourism and other influences around Suncheon-si, which has the facilities for education, tourism and urban locality. Data cleaning is performed on the DB information that is being collected from characterization BIS, which is organized by day of the week, day and month, to analyse the key factors of the traffic flow. If this is utilized by applying a key factor to the real time information, it is expected to provide more reliable and accurate information.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.9
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• pp.699-708
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• 2006

Bus splitting technique reduces bus energy by placing modules with frequent communications closely and using necessary bus segments in communications. But, previous bus splitting techniques can not be used in MPSoC platform, because it uses cache coherency protocol and all processors should be able to see the bus transactions. In this paper, we propose a bus splitting technique for MPSoC platform to reduce bus energy. The proposed technique divides a bus into several bus segments, some for private memory and others for shared memory. So, it minimizes the bus energy consumed in private memory accesses without producing cache coherency problem. We also propose a task allocation technique considering cache coherency protocol. It allocates tasks into processors according to the numbers of bus transactions and cache coherence protocol, and reduces the bus energy consumption during shared memory references. The experimental results from simulations say the bus splitting technique reduces maximal 83% of the bus energy consumption by private memory accesses. Also they show the task allocation technique reduces maximal 30% of bus energy consumed in shared memory references. We can expect the bus splitting technique and the task allocation technique can be used in multiprocessor platforms to reduce bus energy without interference with cache coherency protocol.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.1
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• pp.47-52
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• 2017

This study is BIT(: Bus Information Terminal) features that take advantage of KEPCO eIoT(: energy Internet of Thing) platform, and it's Network configuration is composed of display terminal device, gateway, platform, and the service server. The key features are parts for processing protocol data between the gateway and the device using LoRa(: Long Range) technology, Intelligent applications and SIP(: Session Initiation Protocol) data handling connected to the Taxi reservation system. And the resource tree provided BIT for the service, which commonly used in the application server and the device.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.4A
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• pp.390-398
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• 2004

This paper describes a study on the automatic generation system of the interface for communication among AMBA bus and IPs with different protocols. Employing an extended STG, the proposed system generates the interface modules required for the communication among IPs with different protocols. For an example system, the interface module for communication between AMBA AHB bus and a video decoder has been generated and verified in its functionality. The area and latency have been compared with the manually designed interface. For burst-mode communication, the generated interface module shows the comparable performance with the manually designed module. For single-mode communication, the generated interface module shows a slightly worse performance than the manually designed module. However, the increased area is negligible considering the size of the IP.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.318-321
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• 2012

This paper presents hybrid power system that consist of Shaft Generators and Diesel Generators, connection of Generator and Bus bar, operating method of Generator and design considerations of control system through parallel operation.

• The Journal of the Korea Contents Association
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• v.6 no.5
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• pp.14-19
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• 2006

In this paper, we describe an arrival time guidance system of circular vehicles using GPS, CDMA and TCP/IP technology. The on-board equipment consists of a GPS receiver and a PDA phone. The on-board equipment sends the current position data of the vehicle to the positioning server via CDMA and Internet. The server predicts the arrival time to the next bus-stop. Any user can lookup the current position and the predicted arrival time of the vehicle utilizing his mobile phone, PDA phone, or Web.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.745-753
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• 2016

This paper presents a fully synthesizable low power interconnect bus for millimeter-scale wireless sensor nodes. A segmented ring bus topology minimizes the required chip real estate with low input/output pad count for ultra-small form factors. By avoiding the conventional open drain-based solution, the bus can be fully synthesizable. Low power is achieved by obviating a need for local oscillators in member nodes. Also, aggressive power gating allows low-power standby mode with only 53 gates powered on. An integrated wakeup scheme is compatible with a power management unit that has nW standby mode. A 3-module system including the bus is fabricated in a 180 nm process. The entire system consumes 8 nW in standby mode, and the bus achieves 17.5 pJ/bit/chip.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.4
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• pp.148-159
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• 2005

We propose a technique for finding the worst case response time (WCRT) of a DMA request that is needed in the schedulability analysis of a whole real-time system. The technique consists of three steps. In the first step, we find the worst case bus usage pattern of each CPU task. Then in the second step, we combine the worst case bus usage pattern of CPU tasks to construct the worst case bus usage pattern of the CPU. This second step considers not only the bus requests made by CPU tasks individually but also those due to preemptions among the CPU tasks. finally, in the third step, we use the worst case bus usage pattern of the CPU to derive the WCRT of DMA requests assuming the fixed-priority bus arbitration protocol. Experimental results show that overestimation of the DMA response time by the proposed technique is within $20\%$ for most DMA request sizes and that the percentage overestimation decreases as the DMA request size increases.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.2
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• pp.33-43
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• 1993

Lock mechanism is essential for synchronization on the multiprocessor systems. Lock mechanism needs to reduce the time for lock operation in low lock contention. Lock mechanism must consider the case of the high lock contention. The conventional lock control scheme in memory results in the increase of bus traffic and memory utilization in lock operation. This paper suggests a lock scheme which stores the lock data in cache and manages it efficiently to reduce the time spent in lock operation when the lock contention is low on a multiprocessor system built on HiPi-bus(Highly Pipelined bus). This paper also presents the design of the HIPi-CLOCK (Highly Pipelined bus Cache LOCK mechanism) which transfere the data from on cache to another when the lock contention is high. The designed simulator compares the conventional lock scheme which controls the lock in memory with the suggested HiPi-CLOCK scheme in terms of the RMW(Read-Modify-Write) operation time using simulated trace. It is shown that the suggested lock control scheme performance is over twice than that of the conventional method in low lock contention. When the lock contention is high, the performance of the suggested scheme increases as the number of the shared lock data increases.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.149-152
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• 2005

The DC power-bus' resonance is frequently attributed to EMI sources in the PCBs. Subsequently, it will ruin the digital signal integrity within one system or between adjacent systems in the form of conducted or radiated emission. Hence, since it is of importance to examine the PCB's emission, this paper sheds a light on the radiated emission from the power-bus with regards to its resonance modes. A full-wave analysis method is used to calculate the impedance and radiated electric fields and is validated by physics and an EM analysis tool.