• ETRI Journal
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• v.39 no.5
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• pp.632-642
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• 2017

Digital all-optical parallel computing is an important research direction and spans conventional devices and convergent nano-optics deployments. Optical bus-based interconnects provide interesting aspects such as relative information communication speed-up or slow-down between optical signals. This aspect is harnessed in the newly proposed All-Optical Linear Array with a Reconfigurable Pipelined Bus System (OLARPBS) model. However, the physical realization of such communication interconnects needs to be considered. This paper considers spatial layouts of processing elements along with the optical bus light paths that are necessary to realize the corresponding interconnection requirements. A metric in terms of the degree of required physical constraint is developed to characterize the variety of possible solutions. Simple algorithms that determine spatial layouts are given. It is shown that certain communication interconnection structures have associated intrinsic topologies.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.80-86
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• 2010

The conventional bus system architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. As several masters can't use a bus concurrently, arbiter plays an role in arbitrating the bus. The efficiency of bus usage can be determined by the selection of arbitration method. Fixed Priority, Round-Robin, TDMA and Lottery arbitration policies are studied in the conventional arbitration method where the bus priority is primarily considered. In this paper, we propose the arbitration method that calculates the bus utilization of each master. Furthermore, we verify the performance compared with the other arbitration methods through TLM(Transaction Level Model). From the results of performance verification, the arbitration methods of Fixed Priority and Round-Robin can not set the bus utilization and those of TDMA and Lottery happen the error of 50% and 70% respectively compared with bus utilization set by user in more than 100,000 cycles. On the other hand, the bandwidth-award bus arbitration method remains the error of less than 1% since approximately 1000 cycles, compared with bus utilization set by user.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.38 no.1
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• pp.167-174
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• 2018

This study attempts to construct a model of optimal headway, focusing on a practical applicability to bus transit operation. Examining the existing bus operation and scheduling plans imposed by Busan City, we found that the plans failed to reasonably take into account such realities as varying traffic and operational conditions. The model is thus developed to derive the hourly optimal headway by routes satisfying the real-world conditions: varying hourly demand and cycle time, applying the model to routes 10 and 27 as examples. To do so, we collect big-dataset generated by smart card system and BIMS (Bus Inforamtion Management System). It is expected that the results of this study wil be a basis for further refined research in this field as well as for preparing practical timetables for bus operation.

• Journal of Korean Society of Transportation
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• v.20 no.1
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• pp.7-18
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• 2002

To activate public transportation service, Bucheon City built Bus Information System based on Beacon type, and operates it for no.22 line. This research analyzes an effect of BIS operations, and mainly it analyzes far reliability evaluation of bus arrival time information and passenger satisfaction about BIS. As results of reliability evaluation of arrival time information service, it is proven to be practically inappropriate to use as arrival time data because it is not only travel time between each bus stop but also previous travel time history data. In order to improve this matter, neural network model was evaluated as the most outstanding one as result of experiment in applying current arrival time Prediction model. This research cannot help limiting for evaluation of operation effect in Bucheon City because there is no Bus Information System based on GPS type in Korea. For the future ITS model city, in the case of building ITS model city based on GPS type, it is possible to compare two systems relatively. In addition to that, fur the consideration of reliability of bus arrival time information, it is required to develop Predictable model and research factors that affect to bus operation.

• Proceedings of the KIEE Conference
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• 2000.07a
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• pp.66-68
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• 2000

The Eigen analysis in large power system provides much useful information that is not got in nose curve. The branch participation factor is not quantitative information and is an indirect method calculating incremental change in branch reactive loss. But the Eigen sensitivity analysis to each mode is direct and provides of quantitative information but this method because of needing much time is used in large power system. In this paper the Hessenberg method is used to obtaining dominant eignvalues and corresponding eigenvectors of Jacobian matrix. Ranking the critical contingencies is done by computing the Eigen sensitivity of each dominant eignvalues for changes of each line. The proposed algorithm is tested on the New England 30-bus system and KEPCO system in the year of 2000, which comprises of 791-bus and 2500-branches.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.9
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• pp.1073-1082
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• 1999

본 논문에서는 시스템 내의 프로세서들을 효과적으로 사용하기 위한 적응적 프로세서 할당 정책을 제안한다. 프로그램의 병렬성을 향상시키기 위하여 일반적으로 병렬 처리에 사용될 프로세서 개수를 증가시킨다. 그러나 증가된 프로세서들은 그레인 크기에 변화를 일으키며 이는 캐쉬 성능에 영향을 미친다. 특히 대역이 제한된 공유 버스를 사용하는 시스템에서는 프로세서 개수의 증가는 공유 버스에 대한 접근 경쟁을 크게 증가하므로 버스에서 대기하는 시간이 프로세서 증가에 의한 계산 능력 이득을 상쇄시키는 주요한 원인이 되고 있다. 본 논문에서 제안한 적응적 프로세서 할당 정책은 프로그램이 수행되는 도중에 임의의 기간동안 공유버스에 대기중인 프로세서 분포에 관한 정보를 얻는다. 그리고 이 정보를 바탕으로 프로세서 개수를 변경하는 방법이다. 모의 시험에서 적응적 프로세서 할당 정책은 프로그램들의 버스 트래픽 특성에 따른 최적의 적합한 프로세서 개수를 발견함을 보인다. 그리고 적응적 프로세서 할당 정책은 고정된 프로세서 개수를 사용한 가장 좋은 성능보다는 다소 떨어진 성능을 나타내었으나 시스템의 프로세서 활용성을 높여 효과적 시스템 사용에 기여함을 보인다. Abstract In this paper, the adaptive processor allocation policy is suggested to make effective use of processors in system. To enhance the parallelism, the number of processors used in the parallel computing may be increased. However, increasing the number of processors affects the grain size of the parallel program. Therefore, it affects the cache performance. In particular, when the shared bus is employed, since increasing the number of processors can result in a significant amount of contention to achieve the shared-bus, the increased computing power is offset by the bus waiting time due to these contentions. The adaptive processor allocation policy acquires the information about the distribution of waiting processors on shared bus for any execution period of programs. And it changes the number of processors working in parallel processing during the program's run. Our simulation results show that the adaptive processor allocation policy finds the optimum feasible number of processors based on the bus traffic characteristic of programs. Thus, it contributes to effective system utilization, even though it performs slightly less efficiently than using a fixed number of processors with the best performance.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.31 no.3D
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• pp.375-381
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• 2011

This study presents an analysis of $CO_2$ emission reduction effect on bus information system (BIS) which is operated to improve various services of bus transit such as rapid and on-time service. Although the Intergovernmental Panel on Climate Change (IPCC) released three methodological types of models for analyzing the amount of greenhouse gas reduction, this study used the Tier 3 method that is the most concrete one. A case study was performed to a 8.3 km section of Daejun-Chungjoo BIS system, and dataset required to the Tier 3 method was obtained from ITS-based surveillance systems. The study result showed that the reduction effect of $CO_2$ on BIS operation was yearly $39.45tCO_2/km$. Therefore, such effect can be potentially useful to a measurement of effectiveness (MOE) of BIS projects hereafter.

• Journal of Platform Technology
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• v.11 no.3
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• pp.3-11
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• 2023

Real-time control systems are growing rapidly as infrastructure technologies such as IoT and mobile communication develop and services that value real-time such as factory management and vehicle operation checks increase. Various solutions have been proposed to increase the time sensitivity of this system, but most real-time control systems are currently composed of local servers and multiple clients located in control stations, which are transmitted to local servers where control systems are located. In this paper, we proposed an edge computing-based real-time control model that can reduce the time it takes for the bus information system, one of the real-time control systems, to provide the information to the user at the time it collects the information. Simulating the existing model and the edge computing model, the edge computing model confirmed that the cost for users to receive data is reduced from at least 10% to up to 80% compared to the existing model.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.68-75
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• 2016

As the number of cores and IPs increase in multiprocessor system-on-chip (MPSoC), network-on-chip (NoC) has emerged as a promising novel interconnection architecture for its parallelism and scalability. However, minimization of the latency in NoC with legacy bus IPs must be addressed. In this paper, we focus on the latency minimization problem in NoC which accommodates legacy bus protocol based IPs considering the trade-offs between hop counts and path collisions. To resolve this problem, we propose separated address/data network for independent address and data phases of bus protocol. Compared to Mesh and irregular topologies generated by TopGen, experimental results show that average latency and execution time are reduced by 19.46% and 10.55%, respectively.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.8
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• pp.951-957
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• 1999

The saddle node bifurcation (SNB) and the distance voltage instability are valuable information in power system planning and operation. This paper presents a new efficient, robust and unified strategy to compute the SNB by the combined use of the continuation power flow (CPF), Point of Collapse (PoC) method, and the method of a pair of multiple load flow solutions (PMLFS) with Lagrange interpolation utilizing only their advantages: the approximate nose curves and critical loading are determined fast by Lagrange-interpolating two stable and two unstable solutions obtained by using the robust CPF and PMLFS; the exact SNB is computed by the quadratically converging PoC method. The proposed method has been tested on Klos-Kerner 11-bus, New England 30-bus, IEEE 118-bus and KEPCO 791-bus systems. The method is found to be so efficient that computation time for determining the SNB of the KEPCO 791-bus system is 17.82 sec by a notebook PC with 300 MHz Pentium processor.