• The Transactions of the Korea Information Processing Society
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• v.5 no.1
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• pp.24-32
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• 1998

The bus contention among bus-based shared-memory multiprocessors limits their performance. In addition, under split bus transaction environment, multiprocessors may make some memory requests unnecessary stand by in the memory access buffer, which makes system performance worse. This unnecessary stand-by can be eliminated by maintaining the bitmap table which contains the status bit for each memory block. However, this mechanism requires a great size of SRAM for the status information, which is fully mapped from the whole memory blocks. To solve this problem, we propose a bitmap cache which exploits partial mapping and locality of references. The simulation results show that the proposed system can greatly reduce the capacity of SRAM for the status information with little deteriorating its performance.

• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.2
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• pp.126-133
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• 2022

This study proposes a suppression of zero sequence current (ZSC), which is caused by zero sequence voltage (ZSV) for a dual two-level inverter with single DC bus. Large output voltages enable the dual inverter with single DC bus to improve a system efficiency compared with single inverter. However, the structure of dual inverter with single DC bus inevitably generates ZSC, which reduces the system efficiency and causes a current ripple. ZSV is also produced by dead time, and its magnitude is determined by the DC bus and current direction. This study presents a novel space vector modulation method that allows the instantaneous suppression of ZSC. Based on a condition where a switching period is twice a sampling (control) period, the proposed control method is implemented by injecting the offset voltage at the primary inverter. This offset voltage is injected in half of the switching period to suppress the ZSC. Simulation and experiments are used to compare the proposed and conventional methods to determine the ZSC suppression performance.

• Journal of Digital Convergence
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• v.15 no.10
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• pp.63-81
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• 2017

Objectives of this study are to analyze the previous research perfomed in the Bus Information System (BIS) area and to suggest future research directions. This is a very meaningful and important work. To accomplish this, this study (1) summarizes the concepts of BIS, (2) establishes a research framework to be used to analyze the previous studies in the area, and (3) identifies and suggest trends and future directions of the BIS research. This study has identified total of 68 article (22 foreign and 46 domestic) using 'Google Scholoar' search engine. Major research results include (1) since non-empirical research is dominant, more explanatory empirical research is needed in the future, (2) research that provides consistent and comprehensive measures for BIS related constructs (e.g., BIS quality) is needed, and (3) impacts on the stakeholders of BIS not reflected in the current research (e.g., bus drivers, administrative agencies) should be analyzed in the future research.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.53 no.11
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• pp.596-603
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• 2004

This paper proposes an expert system based on the pattern recognition method which can enhance the accuracy and effectiveness of real-time bus reconfiguration strategy for the transfer of faulted load when a main transformer fault occurs in the automated substation. The minimum distance classification method is adopted as the pattern recognition method of expert system. The training pattern set is designed MTr by MTr to minimize the searching time for target load pattern which is similar to the real-time load pattern. But the control pattern set, which is required to determine the corresponding bus reconfiguration strategy to these trained load pattern set is designed as one table by considering the efficiency of knowledge base design because its size is small. The training load pattern generator based on load level and the training load pattern generator based on load profile are designed, which are can reduce the size of each training pattern set from max L/sup (m+f)/ to the size of effective level. Here, L is the number of load level, m and f are the number of main transformers and the number of feeders. The one reduces the number of trained load pattern by setting the sawmiller patterns to a same pattern, the other reduces by considering only load pattern while the given period. And control pattern generator based on exhaustive search method with breadth-limit is designed, which generates the corresponding bus reconfiguration strategy to these trained load pattern set. The inference engine of the expert system and the substation database and knowledge base is implemented in MFC function of Visual C++ Finally, the performance and effectiveness of the proposed expert system is verified by comparing the best-first search solution and pattern recognition solution based on diversity event simulations for typical distribution substation.

• Aerospace Engineering and Technology
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• v.3 no.2
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• pp.11-19
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• 2004

A software-controlled unregulated bus system in which the main bus is directly connected to a battery and the duty-ratio for PWM switch is controlled by the on-board satellite software, is usually used for LEO satellites. This paper proposes a new power-stage circuit that can be available for modularization of a power regulator which is used at the software-controlled unregulated bus system satellite. And we analyze the proposed power-stage operation according to its operating modes and verify it by performing software simulation and hardware experiment using prototype. We construct a parallel-module converter which is composed of the proposed power-stage and perform experiment to verify modular characteristics of the proposed power-stage. Finally, we verify the usefulness of the proposed power-stage by comparing above results with those of a parallel-module converter made of conventional power-stage.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.35 no.8
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• pp.773-779
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• 2011

In order to improve fuel economy and emissions, many studies of HEV have been conducted. However, most of these studies concentrate on parallel or power-split HEVs. Series-type HEVs have some advantages over parallel and power-split HEVs. One is that the engine is operated at high efficiency since the engine and the driveshaft are decoupled. Nevertheless, the optimization of the powertrain system of series HEV has not been specifically addressed. We conduct an optimization of the generation system of a series HEV based on the series HEV bus. The main objectives are to simulate the system and to compare the fuel economies of conventional and optimized generation systems.

• The Transactions of the Korea Information Processing Society
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• v.4 no.11
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• pp.2914-2922
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• 1997

For FA (factory automation) and ATE (automatic test equipment) in the industrial area, the standard bus needs to increase the system performance of multiprocessor environment. VME(versa module european package format) bus is appropriated to the standard bus but has features of small package and low board density. Beside, the density of board and semiconductor have grown to become significant issues that affect development time, project cost and field diagnostics. To fit this trend, in this paper, we composed Revision C.1 (IEEE std. P1014-1987) of the integrated environment for the main function such as arbitration, interrupt and interface between, VMEbus and several control modules Also the designed, VME system controller is implemented on FPGA that can be located even into slot 1. The control and function modules are coded with VHDL mid-fixed description method and then those operations are verified by simulation. As a result of experiment, we confirmed the most important that is the operation of Bus timer about Bus error signal should occur within $56{\mu}m$, and both control and function modules have the reciprocal operation correctly. Thus, the constructed VHDL library will be able to apply the system based VMEbus and ASIC design.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.30 no.3D
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• pp.223-229
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• 2010

The bus transfer system has been extended from Seoul to Gyonggi province to provide better Seoul metropolitan area transit service in September, 2008. Moreover, the curved bus routes, except existing rapid bus routes, which cause longer travel time have been straightened out. Also, the Skip Stop operation suggested by passengers has been introduced to main stops in the newly added express bus lines. This study surveyed passengers service satisfaction for the recent adopted bus policies such as the transfer discount system and the express bus system in Seoul Metropolitan area. The survey results may be important foundation for future strategies for improvement. The survey included questionnaires about the importance and the satisfaction level on both quantitative and qualitative factors. The results were statistically analyzed by the modified IPA (Importance-Performance Analysis). As the result of the survey, the newly adopted services such as fare system, fare discount on transferring, travel time savings and increased number of stops are economically feasible and satisfactory, whereas the accessibility to stops, ventilation and air quality in vehicles are the priorities to be improved. Also, the safety and the information system is in need of improvement.

• 제어로봇시스템학회:학술대회논문집
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• 1994.10a
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• pp.251-256
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• 1994

Integration of intelligent robot workcell is now a hot issue in CIM and robotics area. This piper dealt with relatively low-level essential topics, i.e., multi-robot coordination and real-time communication for the integration of intelligent robot workcell. For the coordination of multi-robot system, the tightly-coupled coordination is proposed using the various sensors. In order to handle the numerous communication data, time-critical communication network (Field-bus) is introduced and investigated. Finally, intelligent robot workcell is suggested using the Mini-MAP and Field-bus.

• Proceedings of the KIEE Conference
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• 2001.05a
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• pp.62-64
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• 2001

This paper presents a new loss allocation scheme using power contribution method Power contribution is to find how much power at each generating/1oad bus is contributed to individual load/generating bus. In this paper power contribution is calculated using fundamental circuit theory. In numerical simulation, an illustrative example applying the proposed scheme to 6-bus test system is shown.