• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.21 no.3
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• pp.42-52
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• 2022

Bus Information System (BIS) services are expanding nationwide to small and medium-sized cities, including large cities, and user satisfaction is continuously improving. In addition, technology development related to improving reliability of bus arrival time and improvement research to minimize errors continue, and above all, the importance of information accuracy is emerging. In this study, accuracy performance was evaluated using LSTM, a machine learning method, and compared with existing methodologies such as Kalman filter and neural network. As a result of analyzing the standard error for the actual travel time and predicted values, it was analyzed that the LSTM machine learning method has about 1% higher accuracy and the standard error is about 10 seconds lower than the existing algorithm. On the other hand, 109 out of 162 sections (67.3%) were analyzed to be excellent, indicating that the LSTM method was not entirely excellent. It is judged that further improved accuracy prediction will be possible when algorithms are fused through section characteristic analysis.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.12
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• pp.23-30
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• 1998

We present a partial bus-invert coding scheme for system-level power optimization. In the proposed scheme, we select a sub-group of bus lines involved in bus encoding to avoid unnecessary inversion of bus lines not in the sub-group thereby reducing the total number of bus transitions. We propose a heuristic algorithm that selects the sub-group of bus lines for bus encoding. Experiments on benchmark examples indicate that the partial bus-invert coding reduces the total bus transitions by 62.6% on the average, compared to that of the unencoded patterns. We also compare the performance of the proposed heuristic algorithm with that of simulated annealing, which shows that it is highly efficient.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.96-102
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• 2008

The SoC bus topology is classified to single and multiple bus systems due to bus number. In single bus system, the selected only one master among the masters that try to initiate the bus transaction can execute its data transaction. On the other hand, in multiple bus system, as several buses that can be operated independently are connected with bridge, multiple data can be transferred parallel in each bus. However, In the case of data communication from one bus system to the other, data latency has remarkably increased in multiple bus. Furthermore, the performance of multiple bus can be easily different from master number, slave type and so on. In this paper, the performance of single and multiple bus architecture is compared and quantitatively analysed with the variation of master number and slave type especially a tying SDRAM, SRAM and register with TLM simulation method.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.5
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• pp.1-7
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• 2008

The general bus architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. Specially, as several masters do not concurrently receive the right of bus usage, the arbiter plays an important role in arbitrating between shared bus and masters. Fixed priority, round-robin, TDMA and Lottery methods are developed in general arbitration policies, which lead the efficiency of bus usage in shared bus. On the other hand, the bus architecture can be modified to maximize the system performance. In the paper, we propose the flying master bus architecture that supports the parallel bus communication and analyze its merits and demerits following various arbitration policies that are mentioned above, compared with normal shared bus. From the results of performance verification using TLM(Transaction Level Model), we find that more than 40% of the data communication performance improves, regardless of arbitration policies. As the flying master bus architecture advances its studies and applies various SoCs, it becomes the leading candidate of the high performance bus architecture.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.4
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• pp.286-292
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• 2004

In this paper we present a static performance estimation technique of on-chip bus architectures. The proposed technique requires the static scheduling of function blocks of a task to analyze bus conflicts caused by simultaneous accesses from processing elements to which function blocks are mapped. To apply it to multitask applications, the concurrent execution of the function blocks of different tasks also should be considered. Since tasks are scheduled independently, considering all cases of concurrency in each processing element is impractical. Therefore we make an average estimate on the effects of other tasks with respect to bus request rate and bus access time. The proposed technique was incorporated with our exploration framework for on-chip bus architectures, Its viability and efficiency are validated by a preliminary example.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.117-126
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• 2012

This paper provides a method for compression transmission of on-chip bus data. As the data traffic on on-chip buses is rapidly increasing with enlarged video resolutions, many video processor chips suffer from a lack of bus bandwidth and their IP cores have to wait for a longer time to get a bus grant. In multimedia data such as images and video, the adjacent data signals very often have little or no difference between them. Taking advantage of this point, this paper develops a simple bus data compression method to improve the chip performance and presents its hardware implementation. The method is applied to a Video Codec - 1 (VC-1) decoder chip and reduces the processing time of one macro-block by 13.6% and 10.3% for SD and HD videos, respectively

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1081-1084
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• 1998

In this paper, we propose the bus coding technique for low power consumption. For CMOS circuit most power is dissipated as dynamic power for charging and discharging node capacitances.Though the I/O and bus are likely to have the very large capacitances associated with them and dissipate much of the power dissipated by an IC, they have little beenthe special target for power reduction. The conventional Bus-Invert coding method can't decrease the peak power dissipation by 50% because the additional invert signal line can invoke a transition at the time when Bus-Invert coding isn't used to code original bus data. The proposed technique always constraints the Hamming distance between data transferred sequentially to be below the half of the bus width, and thus decrease the I/O peak power dissipation and the I/O average power dissipation.

• Journal of Korea Society of Industrial Information Systems
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• v.16 no.5
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• pp.45-54
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• 2011

Currently various applications related to bus route are used on smart devices to obtain bus arrival times, and route information. However, applications are unable to provide various ways for users to provide their destination. This study has designed an algorithm based on user's six patterns. An Android application and a server that communicate with each other have been based on the algorithm. The applications and the server use the Google Maps service and location-based information to provide users with possible routes from the starting place to the destination. They also provide user's with users' current position and any transfer information. They provide practical and efficient information, and are easy to use.

• Journal of Korean Society for Geospatial Information Science
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• v.22 no.1
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• pp.41-46
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• 2014

Bus service is easily adjusted to accommodate the changed demand. Despite the flexibility of that, its relocation should overcome the following problems: first, Bus line rearrangement should consider the balance between the demand and the supply to enhance the transit equity among the users scattered around the area that supply against demand imbalances. Second, the existing demand analysed is to crude since the demand was analysed based on TAZ. mainly based on the Dong unit. Utilization of the GWR and GIS-T data can resolve the problem. In this paper, the limitation of the conventional transit demand analysis model is overcome by deploying the GWR model which identifies the transit demand based on the geographic relation between the service location and those of the users. GWR model considers the spatial effect of the bus demand in accordance with the distance to the each bus stops using SCD(Smart Card Data) and BIS(Bus Information System). This demand map was then superimposes with the existing bus route which identified the areas where the balance between demand and supply is severly skewed. since the analysis was computed with SCD and BIS at every bus stops. the shortage and surplus of bus service of entire study area could computed. Further. based on this computational result and considering the entire bus service capacity data. Bus routes optimization from the oversupplied areas to the undersupplied area was illustrated thus this study clearly compared the benefits the GIS.

• Journal of the Semiconductor & Display Technology
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• v.16 no.1
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• pp.81-85
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• 2017

The purpose of this study is to investigate the user satisfaction of kiosk contents installed at bus stops in Seoul. A total of 400 kiosks, which are touch-based traffic information systems, are installed and operated, providing contents such as bus routes, marginal area, seoul tourism, life information, angel donation, transportation cards, magnifier and boarding requests. The study results showed that the user satisfaction scores of bus routes and transportation cards were high, but it was necessary to improve other contents. The results of this study will be used as basic data to propose user experience(UX) of public service design. We will also use it as content guidelines for public information kiosks to be developed in the future.