• Journal of IKEEE
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• v.24 no.3
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• pp.845-852
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• 2020

Developing standard cells for 3nm and beyond requires significant advances in the device and interconnect technology. Thus, it is very important to quantify the impact of the new technology in various aspects. In this paper, we perform a through analysis on the impact of Buried Power Rail (BPR) and Complementary FET (CFET) in the perspective of cell area and parasitics such as capacitance. We emphasize that CFET is a technology that realizes 4T and beyond for standard cell designs, but significant capacitance increases (+18.0%), compared to its counterpart technology (FinFET) cell, due to the increase of cell height in the Z-direction.