• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.40 no.6
• /
• pp.1-8
• /
• 2003

A novel CORDIC circuit is presented based on a redundant number system eliminating global carry Propagation. The number format employs a new recoding scheme similar to the Booth receding resolving carry problems in addition. A pipelined architecture is introduced having a constant scale factor in its computation of trigonometric functions. The operational time of the circuit is constant independent of the number of operand digits.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.4 no.5
• /
• pp.1143-1150
• /
• 2000

A dual-mode multiplier (DMM) that performs single- and double-precision multiplications has been designed using a $0.25-\mum$ 5-metal CMOS technology. An algorithm for efficiently implementing double-precision multiplication with a single-precision multiplier was proposed, which is based on partitioning double-precision multiplication into four single-precision sub-multiplications and computing them with sequential accumulations. When compared with conventional double-precision multipliers, our approach reduces the hardware complexity by about one third resulting in small silicon area and low-power dissipation at the expense of increased latency and throughput cycles. The DMM consists of a $28-b\times28-b$ single-precision multiplier designed using radix-4 Booth receding and redundant binary (RB) arithmetic, an accumulator and a simple control logic for mode selection. It contains about 25,000 transistors on the area of about $0.77\times0.40-m^2$. The HSPICE simulation results show that the DMM core can safely operate with 200-MHZ clock at 2.5-V, and its estimated power dissipation is about 130-㎽ at double-precision mode.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.12 no.2
• /
• pp.35-44
• /
• 2002

In this paper, an implementation method of RSA exponentiator based on Radix-$2^k$ modular multiplication algorithm is presented and verified. We use Booth receding algorithm to implement Radix-$2^k$ modular multiplication and implement radix-16 modular multiplier using 2K-byte memory and CSA(carry-save adder) array - with two full adder and three half adder delays. For high speed final addition we use a reduced carry generation and propagation scheme called pseudo carry look-ahead adder. Furthermore, the optimum value of the radix is presented through the trade-off between the operating frequency and the throughput for given Silicon technology. We have verified 1,024-bit RSA processor using Altera FPGA EP2K1500E device and Samsung 0.3$\mu\textrm{m}$ technology. In case of the radix-16 modular multiplication algorithm, (n+4+1)/4 clock cycles are needed and the 1,024-bit modular exponentiation is performed in 5.38ms at 50MHz.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.8 no.6
• /
• pp.1212-1217
• /
• 2004

The main back-bone operation in elliptic curve cryptosystems is scalar point multiplication. The most frequently used method implementing the scalar point multiplication, which is performed in the upper level of GF multiplication and GF division, has been the double-and-add algorithm, which is recently challenged by NAF(Non-Adjacent Format) algorithm. In this paper, we propose a more efficient and novel scalar multiplication method than existing double-and-add by applying redundant receding which originates from radix-4 Booth's algorithm. After deriving the novel quad-and-add algorithm, we created a new operation, named point quadruple, and verified with real application calculation to utilize it. Derived numerical expressions were verified using both C programs and HDL (Hardware Description Language) in real applications. Proposed method of elliptic curve scalar point multiplication can be utilized in many elliptic curve security applications for handling efficient and fast calculations.