A Design of PFC Circuit for Reducing the Harmonic in Constant Voltage-fed Electronic Ballast Circuit (정전압형 전자식 안정기 회로의 고조파 저감을 위한 PFC회로의 설계)
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- Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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- v.18 no.4
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- pp.41-48
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- 2004